PIC18F-LF1XK50 Datasheet, PDF (277/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

PIC18F/LF1XK50
23.0 RESET
The PIC18F/LF1XK50 devices differentiate between
various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 3.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 24.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 23-1.
23.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 23-1). The lower five bits of the reg-
ister indicate that a specific Reset event has occurred.
In most cases, these bits can only be cleared by the
event and must be set by the application after the
event. The state of these flag bits, taken together, can
be read to indicate the type of Reset that just occurred.
This is described in more detail in Section 23.6 “Reset
State of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 7.0 “Interrupts”. BOR is covered in
Section 23.4 “Brown-out Reset (BOR)”.
FIGURE 23-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
MCLR
External Reset
MCLRE
( )_IDLE
Sleep
WDT
Time-out
VDD Rise POR Pulse
Detect
VDD
Brown-out
Reset
BOREN
S
OST/PWRT
OST^{(2) 1024 Cycles}
10-bit Ripple Counter
R
OSC1
Chip_Reset
Q
32 s
LFINTOSC
PWRT⁽²⁾ 65.5 ms
11-bit Ripple Counter
Note 1: See Table 23-2 for time-out situations.
2: PWRT and OST counters are reset by POR and BOR. See Sections 23.3 and 23.4.
Enable PWRT
Enable OST⁽¹⁾
 2010 Microchip Technology Inc.
Preliminary
DS41350E-page 277