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PIC18F-LF1XK50 Datasheet, PDF (27/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers
2.12 Two-Speed Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
Oscillator Start-up Timer (OST) and code execution. In
applications that make heavy use of the Sleep mode,
Two-Speed Start-up will remove the OST period, which
can reduce the overall power consumption of the
device.
Two-Speed Start-up mode is enabled by setting the
IESO bit of the CONFIG1H Configuration register. With
Two-Speed Start-up enabled, the device will execute
instructions using the internal oscillator during the
Primary External Oscillator OST period.
When the system clock is set to the Primary External
Oscillator and the oscillator is configured for LP, XT or
HS modes, the device will not execute code during the
OST period. The OST will suspend program execution
until 1024 oscillations are counted. Two-Speed Start-up
mode minimizes the delay in code execution by
operating from the internal oscillator while the OST is
active. The system clock will switch back to the Primary
External Oscillator after the OST period has expired.
Two-speed Start-up will become active after:
• Power-on Reset (POR)
• Power-up Timer (PWRT), if enabled
• Wake-up from Sleep
The OSTS bit of the OSCCON register reports which
oscillator the device is currently using for operation.
The device is running from the oscillator defined by the
FOSC bits of the CONFIG1H Configuration register
when the OSTS bit is set. The device is running from
the internal oscillator when the OSTS bit is clear.
2.13 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
CONFIG1H Configuration register. The FSCM is
applicable to all external oscillator modes (LP, XT, HS,
EC and RC).
PIC18F/LF1XK50
FIGURE 2-6:
External
Clock
FSCM BLOCK DIAGRAM
Clock Monitor
Latch
SQ
LFINTOSC
Oscillator
÷ 64
31 kHz
(~32 s)
488 Hz
(~2 ms)
Sample Clock
RQ
Clock
Failure
Detected
2.13.1 FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 2-6. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire half-
cycle of the sample clock elapses before the primary
clock goes low.
2.13.2 FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSCFIF of the PIR2 register. The OSCFIF flag will
generate an interrupt if the OSCFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation. An automatic
transition back to the failed clock source will not occur.
The internal clock source chosen by the FSCM is
determined by the IRCF<2:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
 2010 Microchip Technology Inc.
Preliminary
DS41350E-page 27