PIC18F-LF1XK50 Datasheet, PDF (288/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

PIC18F/LF1XK50
TABLE 23-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Address
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
IPR2
PIR2
PIE2
IPR1
PIR1
FA2h
FA1h
FA0h
F9Fh
F9Eh
1111 111-
0000 000-
0000 000-
-111 1111
-000 0000
1111 111-
0000 000-
0000 000-
-111 1111
-000 0000
uuuu uuu-
uuuu uuu-⁽¹⁾
uuuu uuu-
-uuu uuuu
-uuu uuuu⁽¹⁾
PIE1
F9Dh
-000 0000
-000 0000
-uuu uuuu
OSCTUNE
F9Bh
0000 0000
0000 0000
uuuu uuuu
TRISC
F95h
1111 1111
1111 1111
uuuu uuuu
TRISB
F94h
1111 ----
1111 ----
uuuu ----
TRISA
F93h
--11 ----
--11 ----
--uu ----
LATC
F8Bh
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATB
F8Ah
xxxx ----
uuuu ----
uuuu ----
LATA
F89h
--xx ----
--uu ----
--uu ----
PORTC
F82h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
F81h
xxxx ----
uuuu ----
uuuu ----
PORTA
ANSELH⁽⁵⁾
F80h
F7Fh
--xx x-xx
---- 1111
--xx x-xx
---- 1111
--uu u-uu
---- uuuu
ANSEL
F7Eh
1111 1---
1111 1---
uuuu u---
IOCB
F7Ah
0000 ----
0000 ----
uuuu ----
IOCA
F79h
--00 0-00
--00 0-00
--uu u-uu
WPUB
F78h
1111 ----
1111 ----
uuuu ----
WPUA
F77h
--11 1---
--11 1---
--uu u---
SLRCON
F76h
---- -111
---- -111
---- -uuu
SSPMSK
F6Fh
1111 1111
1111 1111
uuuu uuuu
CM1CON0
F6Dh
0000 0000
0000 0000
uuuu uuuu
CM2CON1
F6Ch
0000 0000
0000 0000
uuuu uuuu
CM2CON0
F6Bh
0000 0000
0000 0000
uuuu uuuu
SRCON1
F69h
0000 0000
0000 0000
uuuu uuuu
SRCON0
F68h
0000 0000
0000 0000
uuuu uuuu
UCON
F64h
-0x0 000-
-0x0 000-
-uuu uuu-
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
See Table 23-3 for Reset value for specific condition.
All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
DS41350E-page 288
Preliminary
 2010 Microchip Technology Inc.