PIC18F-LF1XK50 Datasheet, PDF (141/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

PIC18F/LF1XK50
REGISTER 15-2: SSPCON1: MSSP CONTROL 1 REGISTER (SPI MODE)
R/W-0
WCOL
bit 7
R/W-0
SSPOV
R/W-0
SSPEN
R/W-0
CKP
R/W-0
SSPM3
R/W-0
SSPM2
R/W-0
SSPM1
R/W-0
SSPM0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared by software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit⁽¹⁾
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over-
flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared by software).
0 = No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit⁽²⁾
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4
bit 3-0
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
SSPM<3:0>: Synchronous Serial Port Mode Select bits⁽³⁾
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note 1:
2:
3:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
When enabled, these pins must be properly configured as input or output.
Bit combinations not specifically listed here are either reserved or implemented in I²C mode only.
 2010 Microchip Technology Inc.
Preliminary
DS41350E-page 141