PIC18F-LF1XK50 Datasheet, PDF (232/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

PIC18F/LF1XK50
18.8 Additional Comparator Features
There are four additional comparator features:
• Simultaneous read of comparator outputs
• Internal reference selection
• Hysteresis selection
• Output Synchronization
18.8.1 SIMULTANEOUS COMPARATOR
OUTPUT READ
The MC1OUT and MC2OUT bits of the CM2CON1
register are mirror copies of both comparator outputs.
The ability to read both outputs simultaneously from a
single register eliminates the timing skew of reading
separate registers.
Note 1: Obtaining the status of C1OUT or
C2OUT by reading CM2CON1 does not
affect the comparator interrupt mismatch
registers.
18.8.2 INTERNAL REFERENCE
SELECTION
There are two internal voltage references available to
the non-inverting input of each comparator. One of
these is the Fixed Voltage Reference (FVR) and the
other is the variable Comparator Voltage Reference
(CVREF). The CxRSEL bit of the CM2CON register
determines which of these references is routed to the
Comparator Voltage reference output (CXVREF). Fur-
ther routing to the comparator is accomplished by the
CxR bit of the CMxCON0 register. See Section 21.1
“Voltage Reference” and Figure 18-2 and Figure 18-3
for more detail.
18.8.3 COMPARATOR HYSTERESIS
The Comparator Cx have selectable hysteresis. The
hysteresis can be enable by setting the CxHYS bit of
the CM2CON1 register. See Section 27.0 “Electrical
Specifications” for more details.
18.8.4 SYNCHRONIZING COMPARATOR
OUTPUT TO TIMER 1
The Comparator Cx output can be synchronized with
Timer1 by setting the CxSYNC bit of the CM2CON1
register. When enabled, the Cx output is latched on
the rising edge of the Timer1 source clock. If a pres-
caler is used with Timer1, the comparator output is
latched after the prescaling function. To prevent a
race condition, the comparator output is latched on
the rising edge of the Timer1 clock source and Timer1
increments on the rising edge of its clock source. See
the Comparator Block Diagram (Figure 18-2 and
Figure 18-3) and the Timer1 Block Diagram
(Figure 18-2) for more information.
DS41350E-page 232
Preliminary
 2010 Microchip Technology Inc.