PIC18F-LF1XK50 Datasheet, PDF (287/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

PIC18F/LF1XK50
TABLE 23-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Address
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
FC4h
FC3h
FC2h
FC1h
FC0h
FBFh
FBEh
xxxx xxxx
xxxx xxxx
--00 0000
---- 0000
0-00 0000
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
--00 0000
---- 0000
0-00 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
---- uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
CCP1CON
REFCON2
REFCON1
REFCON0
PSTRCON
BAUDCON
PWM1CON
FBDh
FBCh
FBBh
FBAh
FB9h
FB8h
FB7h
0000 0000
---0 0000
000- 00-0
0001 00--
---0 0001
0100 0-00
0000 0000
0000 0000
---0 0000
000- 00-0
0001 00--
---0 0001
0100 0-00
0000 0000
uuuu uuuu
---u uuuu
uuu- uu-u
uuuu uu--
---u uuuu
uuuu u-uu
uuuu uuuu
ECCP1AS
FB6h
0000 0000
0000 0000
uuuu uuuu
TMR3H
FB3h
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
FB2h
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
FB1h
0000 0000
uuuu uuuu
uuuu uuuu
SPBRGH
FB0h
0000 0000
0000 0000
uuuu uuuu
SPBRG
FAFh
0000 0000
0000 0000
uuuu uuuu
RCREG
FAEh
0000 0000
0000 0000
uuuu uuuu
TXREG
FADh
0000 0000
0000 0000
uuuu uuuu
TXSTA
FACh
0000 0010
0000 0010
uuuu uuuu
RCSTA
FABh
0000 000x
0000 000x
uuuu uuuu
EEADR
FAAh
0000 0000
0000 0000
uuuu uuuu
EEDATA
FA8h
0000 0000
0000 0000
uuuu uuuu
EECON2
FA7h
0000 0000
0000 0000
0000 0000
EECON1
FA6h
xx-0 x000
uu-0 u000
uu-0 u000
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
See Table 23-3 for Reset value for specific condition.
All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
 2010 Microchip Technology Inc.
Preliminary
DS41350E-page 287