PIC18F-LF1XK50 Datasheet, PDF (255/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

22.2.2.2 Internal Pull-up Resistors
The PIC18F1XK50/PIC18LF1XK50 devices have
built-in pull-up resistors designed to meet the require-
ments for low-speed and full-speed USB. The UPUEN
bit (UCFG<4>) enables the internal pull-ups.
Figure 22-1 shows the pull-ups and their control.
Note:
The official USB specifications require
that USB devices must never source any
current onto the +5V VBUS line of the USB
cable. Additionally, USB devices must
never source any current on the D+ and
D- data lines whenever the +5V VBUS line
is less than 1.17V. In order to meet this
requirement, applications which are not
purely bus powered should monitor the
VBUS line and avoid turning on the USB
module and the D+ or D- pull-up resistor
until VBUS is greater than 1.17V. VBUS can
be connected to and monitored by any 5V
tolerant I/O pin for this purpose.
22.2.2.3 External Pull-up Resistors
External pull-up may also be used. The VUSB pin may be
used to pull up D+ or D-. The pull-up resistor must be
1.5 k (±5%) as required by the USB specifications.
Figure 22-2 shows an example.
FIGURE 22-2:
PIC^®
Microcontroller
EXTERNAL CIRCUITRY
Host
Controller/HUB
VUSB
PIC18F/LF1XK50
22.2.2.4 Ping-Pong Buffer Configuration
The usage of ping-pong buffers is configured using the
PPB<1:0> bits. Refer to Section 22.4.4 “Ping-Pong
Buffering” for a complete explanation of the ping-pong
buffers.
22.2.2.5 Eye Pattern Test Enable
An automatic eye pattern test can be generated by the
module when the UCFG<7> bit is set. The eye pattern
output will be observable based on module settings,
meaning that the user is first responsible for configuring
the SIE clock settings, pull-up resistor and Transceiver
mode. In addition, the module has to be enabled.
Once UTEYE is set, the module emulates a switch from
a receive to transmit state and will start transmitting a
J-K-J-K bit sequence (K-J-K-J for full speed). The
sequence will be repeated indefinitely while the Eye
Pattern Test mode is enabled.
Note that this bit should never be set while the module
is connected to an actual USB system. This Test mode
is intended for board verification to aid with USB certi-
fication tests. It is intended to show a system developer
the noise integrity of the USB signals which can be
affected by board traces, impedance mismatches and
proximity to other system components. It does not
properly test the transition from a receive to a transmit
state. Although the eye pattern is not meant to replace
the more complex USB certification test, it should aid
during first order system debugging.
1.5 k
D+
D-
Note: The above setting shows a typical connection
for a full-speed configuration using an on-chip
regulator and an external pull-up resistor.
 2010 Microchip Technology Inc.
Preliminary
DS41350E-page 255