PIC32MX5XX_11 Datasheet, PDF (95/256 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers

TABLE 4-22: FLASH CONTROLLER REGISTER MAP
Bits
31/15
30/14
29/13 28/12
27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
F400 NVMCON^{(1) 31:16}
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0 WR
WREN WRERR LVDERR LVDSTAT
—
—
—
—
—
—
—
NVMOP<3:0>
0000
31:16
F410 NVMKEY
15:0
NVMKEY<31:0>
0000
0000
F420 NVMADDR^{(1) 31:16}
15:0
NVMADDR<31:0>
0000
0000
31:16
F430 NVMDATA
15:0
NVMDATA<31:0>
0000
0000
F440
NVMSRC
ADDR
31:16
15:0
NVMSRCADDR<31:0>
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-23: SYSTEM CONTROL REGISTER MAP^(1,2)
Bits
31/15 30/14 29/13 28/12 27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
F000 OSCCON
15:0
—
—
PLLODIV<2:0>
COSC<2:0>
—
FRCDIV<2:0>
NOSC<2:0>
— SOSCRDY —
CLKLOCK ULOCK SLOCK
PBDIV<1:0>
SLPEN
CF
PLLMULT<2:0>
0000
UFRCEN SOSCEN OSWEN 0000
31:16
—
F010 OSCTUN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
TUN<5:0>
0000
31:16
—
0000 WDTCON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
—
—
—
—
—
—
—
SWDTPS<4:0>
—
WDTCLR 0000
31:16
—
F600 RCON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
CMR VREGS EXTR
SWR
—
WDTO SLEEP
IDLE
BOR
POR 0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
F610 RSWRST
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SWRST 0000
31:16
F230 SYSKEY _15:0
SYSKEY<31:0>
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
2:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.