PIC32MX5XX_11 Datasheet, PDF (185/256 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers

PIC32MX5XX/6XX/7XX
TABLE 31-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
Param.
No.
Typical⁽³⁾
Max.
Units
Conditions
Operating Current (IDD)^(1,2) for PIC32MX575/675/695/775 Family Devices
DC20
6
DC20b
7
-40ºC,
9
+25ºC,
Code executing from Flash
mA
+85ºC
—
10
+105ºC
4 MHz
DC20a
4
—
Code executing from SRAM
—
DC21
37
40
Code executing from Flash
mA
—
—
DC21a
25
—
Code executing from SRAM
25 MHz
(Note 4)
DC22
64
70
Code executing from Flash
mA
—
—
DC22a
61
—
Code executing from SRAM
60 MHz
(Note 4)
DC23
85
DC23b
90
-40ºC,
98
+25ºC,
Code executing from Flash
mA
+85ºC
—
120
+105ºC
80 MHz
DC23a
85
—
Code executing from SRAM
—
DC25a 125
150
µA
—
+25°C
Operating Current (IDD)^(1,2,5) for PIC32MX534/564/664/764 Family Devices
3.3V
LPRC (31 kHz)
(Note 4)
DC20b
6
9
mA Code executing from Flash
—
—
DC20c
2
—
mA Code executing from SRAM
—
—
4 MHz
DC21b
19
40
mA Code executing from Flash
—
—
DC21c
14
—
mA Code executing from SRAM
—
—
25 MHz
(Note 4)
DC22b
31
70
mA Code executing from Flash
—
—
DC22c
29
—
mA Code executing from SRAM
—
—
60 MHz
(Note 4)
DC23b
39
98
mA Code executing from Flash
—
—
DC23c
39
—
mA Code executing from SRAM
—
—
80 MHz
DC25b 100
150
µA
—
+25°C
3.3V
LPRC (31 kHz)
(Note 4)
Note 1:
A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
2: The test conditions for IDD measurements are as follows: Oscillator mode = EC+PLL with OSC1 driven by
external square wave from rail-to-rail and PBCLK divisor = 1:8. CPU, Program Flash and SRAM data
memory are operational, program Flash memory Wait states = 7, program cache and prefetch are dis-
abled and SRAM data memory Wait states = 1. All peripheral modules are disabled (ON bit = 0). WDT
and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD.
3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
4: This parameter is characterized, but not tested in manufacturing.
5: This information is preliminary.
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DS61156G-page 185