PIC32MX5XX_11 Datasheet, PDF (94/256 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers

TABLE 4-20: COMPARATOR REGISTER MAP⁽¹⁾
Bits
31/15 30/14 29/13 28/12 27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 —
A000 CM1CON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— 0000
15:0 ON
COE
CPOL
—
—
—
—
COUT
EVPOL<1:0>
—
CREF
—
—
CCH<1:0>
00C3
31:16 —
A010 CM2CON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— 0000
15:0 ON
COE
CPOL
—
—
—
—
COUT
EVPOL<1:0>
—
CREF
—
—
CCH<1:0>
00C3
31:16 —
A060 CMSTAT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— 0000
15:0 —
FRZ
SIDL
—
—
—
—
—
—
—
—
—
—
—
C2OUT C1OUT 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
TABLE 4-21: COMPARATOR VOLTAGE REFERENCE REGISTER MAP⁽¹⁾
Bits
31/15 30/14 29/13 28/12 27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 —
—
9800 CVRCON
15:0 ON
—
—
—
—
—
—
—
—
—
— VREFSEL⁽²⁾ BGSEL<1:0>⁽²⁾
—
—
—
—
—
—
CVROE CVRR CVRSS
—
—
CVR<3:0>
— 0000
0100
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
2: These bits are not available on PIC32MX575/675/695/775 devices. On these devices, reset value for CVRCON is 0000.