PIC32MX5XX_11 Datasheet, PDF (100/256 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers

TABLE 4-32:
PORTF REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES⁽¹⁾
Bits
31/15 30/14 29/13 28/12 27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
6140 TRISF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
TRISF5 TRISF4 TRISF3
—
TRISF1 TRISF0 003B
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
6150 PORTF
15:0
—
—
—
—
—
—
—
—
—
—
RF5
RF4
RF3
—
RF1
RF0
xxxx
31:16
—
6160 LATF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
LATF5 LATF4 LATF3
—
LATF1 LATF0 xxxx
31:16
—
6170 ODCF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
ODCF5 ODCF4 ODCF3
—
ODCF1 ODCF0 0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-33:
PORTF REGISTER MAP PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L,
PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L,
PIC32MX764F128L, PIC32MX775F512L AND PIC32MX795F512L DEVICES⁽¹⁾
Bits
31/15 30/14 29/13 28/12 27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
6140 TRISF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
TRISF13 TRISF12
—
—
—
TRISF8
—
—
TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 313F
31:16
—
6150 PORTF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
RF13
RF12
—
—
—
RF8
—
—
RF5
RF4
RF3
RF2
RF1
RF0 xxxx
31:16
—
6160 LATF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
LATF13 LATF12
—
—
—
LATF8
—
—
LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx
31:16
—
6170 ODCF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
ODCF13 ODCF12
—
—
—
ODCF8
—
—
ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.