PIC32MX5XX_11 Datasheet, PDF (101/256 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers

TABLE 4-34:
PORTG REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES⁽¹⁾
Bits
31/15 30/14 29/13 28/12 27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
6180 TRISG
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
TRISG9 TRISG8 TRISG7 TRISG6
—
—
TRISG3 TRISG2
—
—
03CC
31:16
—
6190 PORTG
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
RG9
RG8
RG7
RG6
—
—
RG3
RG2
—
—
xxxx
31:16
—
61A0 LATG
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
LATG9 LATG8 LATG7 LATG6
—
—
LATG3 LATG2
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
61B0 ODCG
15:0
—
—
—
—
—
—
ODCG9 ODCG8 ODCG7 ODCG6
—
—
ODCG3 ODCG2
—
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-35:
PORTG REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES⁽¹⁾
Bits
31/15 30/14 29/13 28/12 27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
6180 TRISG
15:0 TRISG15 TRISG14 TRISG13 TRISG12
—
—
—
—
—
—
—
—
TRISG9 TRISG8 TRISG7 TRISG6
—
—
—
—
—
—
0000
—
TRISG3 TRISG2 TRISG1 TRISG0 F3CF
31:16
—
—
—
—
—
6190 PORTG
15:0 RG15
RG14
RG13
RG12
—
—
—
—
—
—
—
—
RG9
RG8
RG7
RG6
—
—
—
—
—
—
0000
—
RG3
RG2
RG1
RG0 xxxx
31:16
—
—
—
—
—
61A0 LATG
15:0 LATG15 LATG14 LATG13 LATG12
—
—
—
—
—
—
—
—
LATG9 LATG8 LATG7 LATG6
—
—
—
—
—
—
0000
—
LATG3 LATG2 LATG1 LATG0 xxxx
31:16
—
—
—
—
—
61B0 ODCG
15:0 ODCG15 ODCG14 ODCG13 ODCG12
—
—
—
—
—
—
—
—
ODCG9 ODCG8 ODCG7 ODCG6
—
—
—
—
—
—
0000
—
ODCG3 ODCG2 ODCG1 ODCG0 0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.