PIC32MX5XX_11 Datasheet, PDF(40/256 Page) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers

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PIC32MX5XX_11 Datasheet, PDF (40/256 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers

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PIC32MX5XX/6XX/7XX

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number(1)

64-Pin 100-Pin 121-Pin

QFN/TQFP TQFP

XBGA

Pin

Type

Buffer

Type

Description

EMDC

30

EMDIO

49

AERXD0

43

AERXD1

42

AERXD2

â

AERXD3

â

AERXERR

55

AERXDV

â

AECRSDV

44

AERXCLK

â

AEREFCLK

45

AETXD0

59

AETXD1

58

AETXD2

â

AETXD3

â

AETXERR

â

AETXEN

54

AETXCLK

â

AECOL

â

AECRS

â

AEMDC

30

AEMDIO

49

71

C11

O

â Ethernet management data clock(2)

68

E9

I/O

â Ethernet management data(2)

18

G1

I

ST Alternate Ethernet Receive Data 0(2)

19

G2

I

ST Alternate Ethernet Receive Data 1(2)

28

L2

I

ST Alternate Ethernet Receive Data 2(2)

29

K3

I

ST Alternate Ethernet Receive Data 3(2)

1

B2

I

ST Alternate Ethernet receive error input(2)

12

F2

I

ST Alternate Ethernet receive data valid(2)

12

F2

I

ST Alternate Ethernet carrier sense data valid(2)

14

F3

I

ST Alternate Ethernet receive clock(2)

14

F3

I

ST Alternate Ethernet reference clock(2)

47

L9

O

â Alternate Ethernet Transmit Data 0(2)

48

K9

O

â Alternate Ethernet Transmit Data 1(2)

44

L8

O

â Alternate Ethernet Transmit Data 2(2)

43

K7

O

â Alternate Ethernet Transmit Data 3(2)

35

J5

O

â Alternate Ethernet transmit error(2)

67

E8

O

â Alternate Ethernet transmit enable(2)

66

E11

I

ST Alternate Ethernet transmit clock(2)

42

L7

I

ST Alternate Ethernet collision detect(2)

41

J7

I

ST Alternate Ethernet carrier sense(2)

71

C11

O

â Alternate Ethernet Management Data clock(2)

68

E9

I/O

â Alternate Ethernet Management Data(2)

TRCLK

â

91

C5

O

â Trace clock

TRD0

â

97

A3

O

â Trace Data bits 0-3

TRD1

â

96

C3

O

â

TRD2

â

95

C4

O

â

TRD3

â

92

B5

O

â

PGED1

16

25

K2

I/O

ST Data I/O pin for Programming/Debugging

Communication Channel 1

PGEC1

15

24

K1

I

ST Clock input pin for Programming/Debugging

Communication Channel 1

PGED2

18

27

J3

I/O

ST Data I/O pin for Programming/Debugging

Communication Channel 2

PGEC2

17

26

L1

I

ST Clock input pin for Programming/Debugging

Communication Channel 2

MCLR

7

13

F1

I/P

ST Master Clear (Reset) input. This pin is an

active-low Reset to the device.

Legend:

Note 1:

2:

CMOS = CMOS compatible input or output

Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels

O = Output

I = Input

TTL = TTL input buffer

Pin numbers are provided for reference only. See the âPin Diagramsâ section for device pin availability.

See Section 24.0 âEthernet Controllerâ for more information.

DS61156G-page 40

Â© 2009-2011 Microchip Technology Inc.

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