PIC32MX5XX_11 Datasheet, PDF (133/256 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers

PIC32MX5XX/6XX/7XX
12.0 I/O PORTS
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS61120) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
General purpose I/O pins are the simplest of peripher-
als. They allow the PIC^® MCU to monitor and control
other devices. To add flexibility and functionality, some
pins are multiplexed with alternate function(s). These
functions depend on which peripheral features are on
the device. In general, when a peripheral is functioning,
that pin may not be used as a general purpose I/O pin.
Following are some of the key features of this module:
• Individual output pin open-drain enable/disable
• Individual input pin weak pull-up enable/disable
• Monitor selective inputs and generate interrupt
when change in pin state is detected
• Operation during CPU Sleep and Idle modes
• Fast bit manipulation using CLR, SET and INV
registers
Figure 12-1 illustrates a block diagram of a typical
multiplexed I/O port.
FIGURE 12-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
PIO Module
Peripheral Module
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
RD ODC
Data Bus
SYSCLK
WR ODC
RD TRIS
WR TRIS
WR LAT
WR PORT
DQ
CK
ODC
EN ^Q
1
0
0
1
DQ
CK
TRIS
1
EN ^Q
0
DQ
CK
LAT
EN ^Q
Output Multiplexers
I/O Cell
I/O Pin
RD LAT
1
RD PORT
0
Sleep
SYSCLK
Peripheral Input
R
Peripheral Input Buffer
QD
Q CK
QD
Q CK
Synchronization
Legend:
Note:
R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure
for any specific port/peripheral combination may be different than it is shown here.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 133