PIC32MX5XX_11 Datasheet, PDF (110/256 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers

TABLE 4-45:
CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L,
PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES⁽¹⁾
Bits
31/15 30/14 29/13 28/12 27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 —
B000 C1CON
15:0 ON
—
—
FRZ
SIDLE
—
ABAT
REQOP<2:0>
— CANBUSY —
—
—
OPMOD<2:0>
—
—
—
CANCAP
—
—
—
DNCNT<4:0>
— 0480
0000
B010
31:16 —
—
C1CFG
15:0 SEG2PHTS SAM
—
—
—
SEG1PH<2:0>
—
—
—
PRSEG<2:0>
—
WAKFIL
—
—
—
SEG2PH<2:0>
SJW<1:0>
BRP<5:0>
0000
0000
31:16 IVRIE WAKIE CERRIE SERRIE RBOVIE
—
B020 C1INT
—
—
—
—
—
—
MODIE CTMRIE RBIE
TBIE 0000
15:0 IVRIF
WAKIF CERRIF SERRIF RBOVIF
—
—
—
—
—
—
—
MODIF CTMRIF RBIF
TBIF 0000
31:16 —
—
—
—
—
B030 C1VEC
—
—
—
—
—
—
—
—
—
—
— 0000
15:0
—
—
—
FILHIT<4:0>
—
ICODE<6:0>
0040
31:16 —
—
—
—
—
B040 C1TREC
—
—
—
—
—
TXBO
TXBP
RXBP TXWARN RXWARN EWARN 0000
15:0
TERRCNT<7:0>
RERRCNT<7:0>
0000
31:16 FIFOIP31 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP26 FIFOIP25 FIFOIP24 FIFOIP23 FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16 0000
B050 C1FSTAT
15:0 FIFOIP15 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9 FIFOIP8 FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0 0000
B060 C1RXOVF ^{31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000}
15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000
B070
31:16
C1TMR
15:0
CANTS<15:0>
CANTSPRE<15:0>
0000
0000
31:16
B080 C1RXM0
15:0
SID<10:0>
EID<15:0>
-—
MIDE
—
EID<17:16>
xxxx
xxxx
31:16
B090 C1RXM1
15:0
SID<10:0>
EID<15:0>
-—
MIDE
—
EID<17:16>
xxxx
xxxx
31:16
B0A0 C1RXM2
15:0
SID<10:0>
EID<15:0>
-—
MIDE
—
EID<17:16>
xxxx
xxxx
31:16
B0B0 C1RXM3
15:0
SID<10:0>
EID<15:0>
-—
MIDE
—
EID<17:16>
xxxx
xxxx
31:16 FLTEN3
B0C0 C1FLTCON0
15:0 FLTEN1
MSEL3<1:0>
MSEL1<1:0>
FSEL3<4:0>
FSEL1<4:0>
FLTEN2
FLTEN0
MSEL2<1:0>
MSEL0<1:0>
FSEL2<4:0>
FSEL0<4:0>
0000
0000
31:16 FLTEN7
B0D0 C1FLTCON1
15:0 FLTEN5
MSEL7<1:0>
MSEL5<1:0>
FSEL7<4:0>
FSEL5<4:0>
FLTEN6
FLTEN4
MSEL6<1:0>
MSEL4<1:0>
FSEL6<4:0>
FSEL4<4:0>
0000
0000
31:16 FLTEN11
B0E0 C1FLTCON2
15:0 FLTEN9
MSEL11<1:0>
MSEL9<1:0>
FSEL11<4:0>
FSEL9<4:0>
FLTEN10
FLTEN8
MSEL10<1:0>
MSEL8<1:0>
FSEL10<4:0>
FSEL8<4:0>
0000
0000
31:16 FLTEN15
B0F0 C1FLTCON3
15:0 FLTEN13
MSEL15<1:0>
MSEL13<1:0>
FSEL15<4:0>
FSEL13<4:0>
FLTEN14
FLTEN12
MSEL14<1:0>
MSEL12<1:0>
FSEL14<4:0>
FSEL12<4:0>
0000
0000
Legend:
Note 1:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.