PIC32MX5XX_11 Datasheet, PDF (87/256 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers

TABLE 4-17: DMA GLOBAL REGISTER MAP
Bits
31/15 30/14 29/13 28/12 27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
3000 DMACON^{(1) 31:16}
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
— SUSPEND DMABUSY —
—
—
—
—
—
—
—
—
—
—
31:16 —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3010 DMASTAT
15:0
—
—
—
—
—
—
—
—
—
—
—
—
RDWR
DMACH<2:0>⁽²⁾
31:16
3020 DMAADDR
15:0
DMAADDR<31:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
2: DMACH<3> bit is not available on PIC32MX534/564/664/764 devices.
0000
0000
0000
0000
0000
0000
TABLE 4-18: DMA CRC REGISTER MAP⁽¹⁾
Bits
31/15 30/14 29/13 28/12 27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
3030 DCRCCON
BYTO<1:0>
WBO
—
—
BITO
—
—
—
—
—
—
—
— 0000
15:0
—
—
—
PLEN<4:0>
CRCEN CRCAPP CRCTYP
—
—
CRCCH<2:0>
0000
31:16
3040 DCRCDATA
15:0
DCRCDATA<31:0>
0000
0000
31:16
3050 DCRCXOR
15:0
DCRCXOR<31:0>
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.