PIC32MX5XX_11 Datasheet, PDF (49/256 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers

PIC32MX5XX/6XX/7XX
3.0 CPU
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS61113) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site (www.micro-
chip.com/PIC32). Resources for the
MIPS32^® M4K^® Processor Core are
available at http://www.mips.com.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The MIPS32^® M4K^® Processor core is the heart of the
PIC32MX5XX/6XX/7XX family processor. The CPU
fetches instructions, decodes each instruction, fetches
source operands, executes each instruction and writes
the results of instruction execution to the proper
destinations.
3.1 Features
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32 Enhanced Architecture (Release 2)
- Multiply-accumulate and multiply-subtract
instructions
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
for interrupt handlers
- Bit field manipulation instructions
• MIPS16e^® code compression
- 16-bit encoding of 32-bit instructions to
improve code density
- Special PC-relative instructions for efficient
loading of addresses and constants
- SAVE and RESTORE macro instructions for
setting up and tearing down stack frames
within subroutines
- Improved support for handling 8 and 16-bit
data types
• Simple Fixed Mapping Translation (FMT)
mechanism
• Simple dual bus interface
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
interrupt latency
• Autonomous multiply/divide unit
- Maximum issue rate of one 32x16 multiply
per clock
- Maximum issue rate of one 32x32 multiply
every other clock
- Early-in iterative divide. Minimum 11 and
maximum 33 clock latency (dividend (rs) sign
extension-dependent)
• Power control
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
instruction)
- Extensive use of local gated clocks
• EJTAG debug and instruction trace
- Support for single stepping
- Virtual instruction and data address/value
- Breakpoints
- PC tracing with trace compression
FIGURE 3-1:
MIPS^® M4K^® PROCESSOR CORE BLOCK DIAGRAM
CPU
MDU
Execution
Core
(RF/ALU/Shift)
FMT
EJTAG
Trace
TAP
Trace I/F
Off-Chip
Debug I/F
Bus Interface
Dual Bus I/F
System
Coprocessor
Power
Management
© 2009-2011 Microchip Technology Inc.
DS61156G-page 49