PIC32MX5XX_11 Datasheet, PDF (104/256 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers

TABLE 4-40: PREFETCH REGISTER MAP
Bits
31/15 30/14 29/13 28/12 27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
4000 CHECON^{(1,2) 31:16}
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHECOH 0000
15:0
—
—
—
—
—
—
DCSZ<1:0>
—
—
PREFEN<1:0>
—
PFMWS<2:0>
0007
4010 CHEACC^{(1) 31:16 CHEWEN}
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— 0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
CHEIDX<3:0>
0000
4020 CHETAG^{(1) 31:16 LTAGBOOT}
—
—
—
—
—
—
—
15:0
LTAG<15:4>
LTAG<23:16>
LVALID
LLOCK
LTYPE
00xx
— xxx2
4030 CHEMSK^{(1) 31:16}
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— 0000
15:0
LMASK<15:5>
—
—
—
—
— 0000
31:16
4040 CHEW0
15:0
CHEW0<31:0>
xxxx
xxxx
31:16
4050 CHEW1
15:0
CHEW1<31:0>
xxxx
xxxx
31:16
4060 CHEW2
15:0
CHEW2<31:0>
xxxx
xxxx
31:16
4070 CHEW3
15:0
CHEW3<31:0>
xxxx
xxxx
31:16
—
—
—
—
—
—
—
4080 CHELRU
15:0
CHELRU<15:0>
CHELRU<24:16>
0000
0000
31:16
4090 CHEHIT
15:0
CHEHIT<31:0>
xxxx
xxxx
31:16
40A0 CHEMIS
15:0
CHEMIS<31:0>
xxxx
xxxx
31:16
40C0 CHEPFABT
15:0
CHEPFABT<31:0>
xxxx
xxxx
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
2: Reset value is dependent on DEVCFGx configuration.