PIC32MX5XX_11 Datasheet, PDF (111/256 Pages) Microchip Technology – High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers

TABLE 4-45:
CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L,
PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES⁽¹⁾ (CONTINUED)
Bits
31/15 30/14 29/13 28/12 27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 FLTEN19
B100 C1FLTCON4
15:0 FLTEN17
MSEL19<1:0>
MSEL17<1:0>
FSEL19<4:0>
FSEL17<4:0>
FLTEN18
FLTEN16
MSEL18<1:0>
MSEL16<1:0>
FSEL18<4:0>
FSEL16<4:0>
0000
0000
31:16 FLTEN23
B110 C1FLTCON5
15:0 FLTEN21
MSEL23<1:0>
MSEL21<1:0>
FSEL23<4:0>
FSEL21<4:0>
FLTEN22
FLTEN20
MSEL22<1:0>
MSEL20<1:0>
FSEL22<4:0>
FSEL20<4:0>
0000
0000
31:16 FLTEN27
B120 C1FLTCON6
15:0 FLTEN25
MSEL27<1:0>
MSEL25<1:0>
FSEL27<4:0>
FSEL25<4:0>
FLTEN26
FLTEN24
MSEL26<1:0>
MSEL24<1:0>
FSEL26<4:0>
FSEL24<4:0>
0000
0000
31:16 FLTEN31
B130 C1FLTCON7
15:0 FLTEN29
MSEL31<1:0>
MSEL29<1:0>
FSEL31<4:0>
FSEL29<4:0>
FLTEN30
FLTEN28
MSEL30<1:0>
MSEL28<1:0>
FSEL30<4:0>
FSEL28<4:0>
0000
0000
B140
C1RXFn ^31:16
(n = 0-31) _15:0
SID<10:0>
EID<15:0>
-—
EXID
—
EID<17:16>
xxxx
xxxx
31:16
B340 C1FIFOBA
15:0
C1FIFOBA<31:0>
0000
0000
B350
C1FIFOCONn ^31:16
(n = 0-31) _15:0
—
—
31:16 —
B360
C1FIFOINTn
(n = 0-31)
15:0
—
—
FRESET
—
—
—
UINC
—
—
—
DONLY
—
—
—
—
—
—
—
—
—
FSIZE<4:0>
0000
—
—
—
—
TXEN TXABAT TXLARB TXERR TXREQ RTREN
TXPRI<1:0>
0000
— TXNFULLIE TXHALFIE TXEMPTYIE —
—
—
—
RXOVFLIE
RXFULLIE
RXHALFIE
RXN
EMPTYIE
0000
— TXNFULLIF TXHALFIF TXEMPTYIF —
—
—
—
RXOVFLIF
RXFULLIF
RXHALFIF
RXN
EMPTYIF
0000
B370
C1FIFOUAn ^31:16
(n = 0-31) _15:0
C1FIFOUA<31:0>
0000
0000
B380
C1FIFOCIn ^31:16
(n = 0-31) _15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— 0000
—
—
—
C1FIFOCI<4:0>
0000
Legend:
Note 1:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.