PIC24FJ128GA310-I Datasheet, PDF (93/406 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and nanoWatt XLP Technology

PIC24FJ128GA310 FAMILY
TABLE 7-1: RESET FLAG BIT OPERATION
Flag Bit
Setting Event
TRAPR (RCON<15>)
IOPUWR (RCON<14>)
CM (RCON<9>)
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
Trap Conflict Event
Illegal Opcode or Uninitialized W Register Access
Configuration Mismatch Reset
MCLR Reset
RESET Instruction
WDT Time-out
SLEEP (RCON<3>)
DPSLP (RCON<10>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
PWRSAV #0 Instruction
PWRSAV #0 Instruction while DSEN bit set
PWRSAV #1 Instruction
POR, BOR
POR
Note: All Reset flag bits may be set or cleared by the user software.
Clearing Event
POR
POR
POR
POR
POR
CLRWDT, PWRSAV
Instruction, POR
POR
POR
POR
—
—
7.1 Special Function Register Reset
States
Most of the Special Function Registers (SFRs) associ-
ated with the PIC24F CPU and peripherals are reset to a
particular value at a device Reset. The SFRs are
grouped by their peripheral or CPU function and their
Reset values are specified in each section of this manual.
The Reset value for each SFR does not depend on the
type of Reset, with the exception of four registers. The
Reset value for the Reset Control register, RCON, will
depend on the type of device Reset. The Reset value
for the Oscillator Control register, OSCCON, will
depend on the type of Reset and the programmed
values of the FNOSC bits in Flash Configuration
Word 2 (CW2) (see Table 7-2). The RCFGCAL and
NVMCON registers are only affected by a POR.
7.2 Device Reset Times
The Reset times for various types of device Reset are
summarized in Table 7-3. Note that the system Reset
signal, SYSRST, is released after the POR delay time
expires.
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The Fail-Safe Clock Monitor (FSCM) delay determines
the time at which the FSCM begins to monitor the
system clock source after the SYSRST signal is
released.
7.3 Brown-out Reset (BOR)
PIC24FJ128GA310 family devices implement a BOR
circuit that provides the user with several configuration
and power-saving options. The BOR is controlled by
the BOREN (CW3<12>) Configuration bit.
When BOR is enabled, any drop of VDD below the BOR
threshold results in a device BOR. Threshold levels are
described in Section 32.1 “DC Characteristics”
(Parameter DC17).
7.4 Clock Source Selection at Reset
If clock switching is enabled, the system clock source
at device Reset is chosen, as shown in Table 7-2. If
clock switching is disabled, the system clock source is
always selected according to the Oscillator Configura-
tion bits. Refer to the “PIC24F Family Reference
Manual”, Section 6.0 “Oscillator” (DS39700) for
further details.
TABLE 7-2:
Reset Type
POR
BOR
MCLR
WDTO
SWR
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
Clock Source Determinant
FNOSC Configuration bits
(CW2<10:8>)
COSC Control bits
(OSCCON<14:12>)
 2010-2011 Microchip Technology Inc.
DS39996F-page 93