PIC24FJ128GA310-I Datasheet, PDF (75/406 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and nanoWatt XLP Technology

PIC24FJ128GA310 FAMILY
5.0 DIRECT MEMORY ACCESS
CONTROLLER (DMA)
Note:
This data sheet summarizes the features
of the PIC24FJ128GA310 family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
the “PIC24F Family Reference Manual”,
Section 54. “Direct Memory Access
Controller (DMA)” (DS39742). The infor-
mation in this data sheet supersedes the
information in the FRM.
The Direct Memory Access Controller (DMA) is
designed to service high-data-throughput peripherals
operating on the SFR bus, allowing them to access
data memory directly and alleviating the need for CPU
intensive management. By allowing these data inten-
sive peripherals to share their own data path, the main
data bus is also de-loaded, resulting in additional
power savings.
The DMA Controller functions both as a peripheral and
a direct extension of the CPU. It is located on the micro-
controller data bus between the CPU and
DMA-enabled peripherals, with direct access to SRAM.
This partitions the SFR bus into two buses, allowing the
DMA Controller access to the DMA-capable peripher-
als located on the new DMA SFR bus. The controller
serves as a master device on the DMA SFR bus,
controlling data flow from DMA capable peripherals.
The controller also monitors CPU instruction process-
ing directly, allowing it to be aware of when the CPU
requires access to peripherals on the DMA bus, and
automatically relinquishing control to the CPU as
needed. This increases the effective bandwidth for
handling data without DMA operations causing a
processor stall. This makes the controller essentially
transparent to the user.
The DMA Controller has these features:
• Six multiple independent and independently
programmable channels
• Concurrent operation with the CPU (no DMA
caused Wait states)
• DMA bus arbitration
• Five Programmable Address modes
• Four Programmable Transfer modes
• Four Flexible Internal Data Transfer modes
• Byte or word support for data transfer
• 16-Bit Source and Destination Address register
for each channel, dynamically updated and
reloadable
• 16-Bit Transaction Count register, dynamically
updated and reloadable
• Upper and Lower Address Limit registers
• Counter half-full level interrupt
• Software triggered transfer
• Null Write mode for symmetric buffer operations
A simplified block diagram of the DMA Controller is
shown if Figure 5-1.
FIGURE 5-1:
DMA FUNCTIONAL BLOCK DIAGRAM
To I/O Ports
and Peripherals
CPU Execution Monitoring
To DMA-Enabled
Peripherals
Data
Bus
Control
Logic
DMACON
DMAH
DMAL
DMABUF
DMACH0
DMAINT0
DMASRC0
DMADST0
DMACNT0
Channel 0
DMACH1
DMAINT1
DMASRC1
DMADST1
DMACNT1
Channel 1
DMACH2
DMAINT2
DMASRC2
DMADST2
DMACNT2
Channel 4
DMACHn
DMAINTn
DMASRCn
DMADSTn
DMACNTn
Channel 5
Data RAM
Data RAM
Address Generation
 2010-2011 Microchip Technology Inc.
DS39996F-page 75