PIC24FJ128GA310-I Datasheet, PDF (117/406 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and nanoWatt XLP Technology

PIC24FJ128GA310 FAMILY
REGISTER 8-15: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
bit 1
SPI2IE: SPI2 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0
SPF2IE: SPI2 Fault Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
REGISTER 8-16: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
U-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
RTCIE
DMA5IE
—
—
—
—
bit 15
U-0
—
bit 8
U-0
R/W-0
R/W-0
U-0
—
INT4IE⁽¹⁾
INT3IE⁽¹⁾
—
bit 7
U-0
R/W-0
R/W-0
U-0
—
MI2C2IE
SI2C2IE
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5
bit 4-3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
RTCIE: Real-Time Clock/Calendar Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
DMA5IE: DMA Channel 5 Interrupt Flag Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
Unimplemented: Read as ‘0’
INT4IE: External Interrupt 4 Enable bit⁽¹⁾
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
INT3IE: External Interrupt 3 Enable bit⁽¹⁾
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
Unimplemented: Read as ‘0’
MI2C2IE: Master I2C2 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
SI2C2IE: Slave I2C2 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
Unimplemented: Read as ‘0’
Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx
pin. See Section 11.4 “Peripheral Pin Select (PPS)” for more information.
 2010-2011 Microchip Technology Inc.
DS39996F-page 117