PIC24FJ128GA310-I Datasheet, PDF (41/406 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and nanoWatt XLP Technology

PIC24FJ128GA310 FAMILY
4.0 MEMORY ORGANIZATION
As Harvard architecture devices, PIC24F micro-
controllers feature separate program and data memory
spaces and busses. This architecture also allows direct
access of program memory from the data space during
code execution.
4.1 Program Memory Space
The program address memory space of the
PIC24FJ128GA310 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
from either the 23-bit Program Counter (PC) during pro-
gram execution, or from table operation or data space
remapping, as described in Section 4.3 “Interfacing
Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24FJ128GA310 family of
devices are shown in Figure 4-1.
FIGURE 4-1:
PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GA310 FAMILY DEVICES
PIC24FJ64GA3XX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Flash
Program Memory
(22K instructions)
Flash Config Words
PIC24F128GA3XX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Flash
Program Memory
(44K instructions)
Flash Config Words
000000h
000002h
000004h
0000FEh
000100h
000104h
0001FEh
000200h
00ABFEh
00AC00h
0157FEh
015800h
Unimplemented
Read ‘0’
Unimplemented
Read ‘0’
7FFFFEh
800000h
Reserved
Device Config Registers
Reserved
DEVID (2)
Note: Memory areas are not shown to scale.
 2010-2011 Microchip Technology Inc.
Reserved
Device Config Registers
F7FFFEh
F80000h
F8000Eh
F80010h
Reserved
DEVID (2)
FEFFFEh
FF0000h
FFFFFEh
DS39996F-page 41