PIC24FJ128GA310-I Datasheet, PDF (397/406 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and nanoWatt XLP Technology

PIC24FJ128GA310 FAMILY
Interrupts
Control and Status Registers ...................................... 98
Implemented Vectors .................................................. 97
Reset Sequence ......................................................... 95
Setup and Service Procedures ................................. 143
Trap Vectors ............................................................... 96
Vector Table................................................................ 96
J
JTAG Interface .................................................................. 346
K
Key Features..................................................................... 333
L
LCD Controller .................................................................... 12
Liquid Crystal Display (LCD) Controller ............................ 265
M
Memory Organization.......................................................... 41
Microchip Internet Web Site .............................................. 400
Modulator. See Data Signal Modulator. ............................ 249
MPLAB ASM30 Assembler, Linker, Librarian ................... 348
MPLAB Integrated Development
Environment Software............................................... 347
MPLAB PM3 Device Programmer .................................... 350
MPLAB REAL ICE In-Circuit Emulator System................. 349
MPLINK Object Linker/MPLIB Object Librarian ................ 348
N
Near Data Space ................................................................ 44
O
On-Chip Voltage Regulator ............................................... 343
POR .......................................................................... 343
Standby Mode........................................................... 343
Oscillator Configuration
Bit Values for Clock Selection................................... 146
Clock Switching......................................................... 150
Sequence.......................................................... 151
Control Registers ...................................................... 147
CPU Clocking Scheme ............................................. 146
Initial Configuration on POR ..................................... 146
Reference Clock Output............................................ 152
Secondary Oscillator (SOSC) ................................... 152
Output Compare
32-Bit Cascaded Mode ............................................. 211
Synchronous and Trigger Modes.............................. 211
Output Compare with Dedicated Timers ........................... 211
P
Packaging ......................................................................... 377
Details ....................................................................... 379
Marking ..................................................................... 377
Peripheral Pin Select (PPS) .............................................. 173
Available Peripherals and Pins ................................. 173
Configuration Control ................................................ 176
Considerations for Use ............................................. 177
Input Mapping ........................................................... 174
Mapping Exceptions.................................................. 176
Output Mapping ........................................................ 175
Peripheral Priority ..................................................... 173
Registers................................................................... 178
Pin Descriptions
121-Pin Devices (BGA)................................................. 7
Pinout Descriptions ............................................................. 17
Power-Saving Features .................................................... 155
Clock Frequency and Clock Switching ..................... 165
Doze Mode ............................................................... 165
Instruction-Based Modes.......................................... 156
Deep Sleep....................................................... 158
Idle.................................................................... 157
Sleep ................................................................ 157
Low-Voltage
Retention Regulator.......................................... 157
Vbat Mode ................................................................ 160
Product Identification System ........................................... 402
Program Memory
Access Using Table Instructions ................................ 71
Address Construction ................................................. 69
Address Space ........................................................... 41
Flash Configuration Words ......................................... 42
Hard Memory Vectors................................................. 42
Memory Maps............................................................. 41
Organization ............................................................... 42
Reading From Program Memory Using EDS ............. 72
Program Verification ......................................................... 345
Pulse-Width Modulation (PWM) Mode.............................. 213
Pulse-Width Modulation. See PWM.
PWM
Duty Cycle and Period.............................................. 214
R
Reader Response............................................................. 401
Real-Time Clock and Calendar (RTCC) ........................... 275
Register Maps
A/D Converter............................................................. 56
Analog Configuration .................................................. 57
Comparators............................................................... 61
CPU Core ................................................................... 45
CRC............................................................................ 62
CTMU ......................................................................... 57
Data Signal Modulator (DSM)..................................... 61
Deep Sleep................................................................. 64
DMA............................................................................ 58
I²C .............................................................................. 51
ICN ............................................................................. 46
Input Capture.............................................................. 49
Interrupt Controller...................................................... 47
LCD Controller............................................................ 59
NVM............................................................................ 64
Output Compare ......................................................... 50
Pad Configuration....................................................... 55
Parallel Master/Slave Port .......................................... 60
Peripheral Pin Select .................................................. 62
PMD............................................................................ 64
PORTA ....................................................................... 53
PORTB ....................................................................... 53
PORTC ....................................................................... 54
PORTD ....................................................................... 54
PORTE ....................................................................... 54
PORTF ....................................................................... 55
PORTG....................................................................... 55
RTCC.......................................................................... 61
SPI.............................................................................. 53
System Control ........................................................... 63
Timers......................................................................... 48
UART.......................................................................... 52
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