PIC24FJ128GA310-I Datasheet, PDF (80/406 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and nanoWatt XLP Technology

PIC24FJ128GA310 FAMILY
REGISTER 5-2: DMACHn: DMA CHANNEL n CONTROL REGISTER
U-0
U-0
U-0
—
—
—
bit 15
r-0
R/W-0
R/W-0
r
—
NULLW
R/W-0
RELOAD⁽¹⁾
R/W-0
CHREQ⁽³⁾
bit 8
R/W-0
SAMODE1
bit 7
R/W-0
SAMODE0
R/W-0
DAMODE1
R/W-0
DAMODE0
R/W-0
TRMODE1
R/W-0
TRMODE0
R/W-0
SIZE
R/W-0
CHEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-6
bit 5-4
bit 3-2
bit 1
bit 0
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
NULLW: Null Write Mode bit
1 = A dummy write is initiated to DMASRC for every write to DMADST
0 = No dummy write is initiated
RELOAD: Address and Count Reload bit⁽¹⁾
1 = DMASRC, DMADST, and DMACNT registers are reloaded to their previous values upon the start
of the next operation
0 = DMASRC, DMADST and DMACNT are not reloaded on the start of the next operation⁽²⁾
CHREQ: DMA Channel Software Request bit⁽³⁾
1 = A DMA request is initiated by software; automatically cleared upon completion of a DMA transfer
0 = No DMA request is pending
SAMODE<1:0>: Source Address Mode Selection bits
11 = DMASRC is used in Peripheral Indirect Addressing and remains unchanged
10 = DMASRC is decremented based on SIZE bit after a transfer completion
01 = DMASRC is incremented based on SIZE bit after a transfer completion
00 = DMASRC remains unchanged after a transfer completion
DAMODE<1:0>: Destination Address Mode Selection bits
11 = DMADST is used in Peripheral Indirect Addressing and remains unchanged
10 = DMADST is decremented based on SIZE bit after a transfer completion
01 = DMADST is incremented based on SIZE bit after a transfer completion
00 = DMADST remains unchanged after a transfer completion
TRMODE<1:0>: Transfer Mode Selection bits
11 = Repeated Continuous
10 = Continuous
01 = Repeated One-Shot
00 = One-Shot
SIZE: Data Size Selection bit
1 = Byte (8-bit)
0 = Word (16-bit)
CHEN: DMA Channel Enable bit
1 = The corresponding channel is enabled
0 = The corresponding channel is disabled
Note 1:
2:
3:
Only the original DMACNT is required to be stored to recover the original DMASRC and DMADST.
DMASRC, DMADST and DMACNT are always reloaded in Repeated mode transfers (DMACHn<2> = 1),
regardless of the state of the RELOAD bit.
The number of transfers executed while CHREQ is set depends on the configuration of TRMODE<1:0>.
DS39996F-page 80
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