PIC24FJ128GA310-I Datasheet, PDF (229/406 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and nanoWatt XLP Technology

PIC24FJ128GA310 FAMILY
FIGURE 16-3:
SPI MASTER/SLAVE CONNECTION (STANDARD MODE)
Processor 1 (SPI Master)
Processor 2 (SPI Slave)
SDOx
Serial Receive Buffer
(SPIxRXB)
SDIx
Serial Receive Buffer
(SPIxRXB)⁽²⁾
Shift Register
(SPIxSR)
MSb
LSb
SDIx
Serial Transmit Buffer
(SPIxTXB)
SDOx
Shift Register
(SPIxSR)⁽²⁾
MSb
LSb
Serial Transmit Buffer
(SPIxTXB)⁽²⁾
SPIx Buffer
(SPIxBUF)⁽²⁾
SCKx ^{Serial Clock SCKx}
SSx⁽¹⁾
SPIx Buffer
(SPIxBUF)⁽²⁾
MSTEN (SPIxCON1<5>) = 1)
SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0
Note 1: Using the SSx pin in Slave mode of operation is optional.
2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers
are memory mapped to SPIxBUF.
FIGURE 16-4:
SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)
Processor 1 (SPI Enhanced Buffer Master)
SDOx
Processor 2 (SPI Enhanced Buffer Slave)
SDIx
Shift Register
(SPIxSR)
MSb
LSb
SDIx
SDOx
Shift Register
(SPIxSR)
MSb
LSb
8-Level FIFO Buffer
8-Level FIFO Buffer
SPIx Buffer
(SPIxBUF)⁽²⁾
Serial Clock
SCKx
SCKx
SSx
SSx⁽¹⁾
SPIx Buffer
(SPIxBUF)⁽²⁾
MSTEN (SPIxCON1<5>) = 1 and
SPIBEN (SPIxCON2<0>) = 1
SSEN (SPIxCON1<7>) = 1,
MSTEN (SPIxCON1<5>) = 0 and
SPIBEN (SPIxCON2<0>) = 1
Note 1: Using the SSx pin in Slave mode of operation is optional.
2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are
memory mapped to SPIxBUF.
 2010-2011 Microchip Technology Inc.
DS39996F-page 229