PIC24FJ128GA310-I Datasheet, PDF (146/406 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and nanoWatt XLP Technology

PIC24FJ128GA310 FAMILY
9.1 CPU Clocking Scheme
The system clock source can be provided by one of
four sources:
• Primary Oscillator (POSC) on the OSCI and
OSCO pins
• Secondary Oscillator (SOSC) on the SOSCI and
SOSCO pins
• Fast Internal RC (FRC) Oscillator
• Low-Power Internal RC (LPRC) Oscillator
The primary oscillator and FRC sources have the
option of using the internal 4x PLL. The frequency of
the FRC clock source can optionally be reduced by the
programmable clock divider. The selected clock source
generates the processor and peripheral clock sources.
The processor clock source is divided by two to pro-
duce the internal instruction cycle clock, FCY. In this
document, the instruction cycle clock is also denoted
by FOSC/2. The internal instruction cycle clock, FOSC/2,
can be provided on the OSCO I/O pin for some
operating modes of the primary oscillator.
9.2 Initial Configuration on POR
The oscillator source (and operating mode) that is
used at a device Power-on Reset event is selected
using Configuration bit settings. The Oscillator
Configuration bit settings are located in the
Configuration registers in the program memory (refer
to Section 29.0 “Special Features” for further
details). The Primary Oscillator Configuration bits,
POSCMD<1:0> (Configuration Word 2<1:0>), and
the Initial Oscillator Select Configuration bits,
FNOSC<2:0> (Configuration Word 2<10:8>), select
the oscillator source that is used at a Power-on Reset.
The FRC Primary Oscillator (FRCDIV) with postscaler
is the default (unprogrammed) selection. The second-
ary oscillator, or one of the internal oscillators, may be
chosen by programming these bit locations.
The Configuration bits allow users to choose between
the various clock modes, shown in Table 9-1.
9.2.1
CLOCK SWITCHING MODE
CONFIGURATION BITS
The FCKSM Configuration bits (Configuration
Word 2<7:6>) are used to jointly configure device clock
switching and the Fail-Safe Clock Monitor (FSCM).
Clock switching is enabled only when FCKSM1 is
programmed (‘0’). The FSCM is enabled only when the
FCKSM<1:0> bits are both programmed (‘00’).
TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator Source POSCMD<1:0>
FNOSC<2:0>
Fast RC Oscillator with Postscaler
Internal
11
111
(FRCDIV)
(Reserved)
Internal
xx
110
Low-Power RC Oscillator (LPRC)
Internal
11
101
Secondary (Timer1) Oscillator
Secondary
11
100
(SOSC)
Primary Oscillator (XT) with PLL
Primary
01
011
Module (XTPLL)
Primary Oscillator (EC) with PLL
Primary
00
011
Module (ECPLL)
Primary Oscillator (HS)
Primary
10
010
Primary Oscillator (XT)
Primary
01
010
Primary Oscillator (EC)
Primary
00
010
Fast RC Oscillator with PLL Module
Internal
11
001
(FRCPLL)
Fast RC Oscillator (FRC)
Internal
11
000
Note 1: OSCO pin function is determined by the OSCIOFCN Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
Note
1, 2
1
1
1
1
1
DS39996F-page 146
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