PIC24FJ128GA310-I Datasheet, PDF (302/406 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and nanoWatt XLP Technology

PIC24FJ128GA310 FAMILY
REGISTER 24-2: AD1CON2: A/D CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
PVCFG1
PVCFG0
NVCFG0
OFFCAL BUFREGEN CSCNA
—
bit 15
U-0
—
bit 8
R/W-0
BUFS⁽¹⁾
bit 7
R/W-0
SMPI4
R/W-0
SMPI3
R/W-0
SMPI2
R/W-0
SMPI1
R/W-0
SMPI0
R/W-0
BUFM⁽¹⁾
R/W-0
ALTS
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6-2
PVCFG<1:0>: Converter Positive Voltage Reference Configuration bits
1x = Unimplemented, do not use
01 = External VREF+
00 = AVDD
NVCFG0: Converter Negative Voltage Reference Configuration bits
1 = External VREF-
0 = AVSS
OFFCAL: Offset Calibration Mode Select bit
1 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to AVSS
0 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to normal inputs
BUFREGEN: A/D Buffer Register Enable bit
1 = Conversion result is loaded into the buffer location determined by the converted channel
0 = A/D result buffer is treated as a FIFO
CSCNA: Scan Input Selections for CH0+ During Sample A bit
1 = Scan inputs
0 = Do not scan inputs
Unimplemented: Read as ‘0’
BUFS: Buffer Fill Status bit⁽¹⁾
1 = A/D is filling the upper half of the buffer; user should access data in the lower half
0 = A/D is filling the lower half of the buffer; user should access data in the upper half
SMPI<4:0>: Interrupt Sample/DMA Increment Rate Select bits
When DMAEN = 1:
0001 = For 2-channel DMA A/D operation
0000 = For 1-channel DMA A/D operation
When DMAEN = 0:
Selects the number of sample/conversions per each interrupt
11111 = Interrupt/address increment at the completion of conversion for each 32nd sample
11110 = Interrupt/address increment at the completion of conversion for each 31st sample

00001 = Interrupt/address increment at the completion of conversion for every other sample
00000 = Interrupt/address increment at the completion of conversion for each sample
Note 1: These bits are only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS
is only used when BUFM = 1.
DS39996F-page 302
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