PIC24FJ128GA310-I Datasheet, PDF (159/406 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and nanoWatt XLP Technology

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10.4.2 EXITING DEEP SLEEP MODES
Deep Sleep modes exit on any one of the following events:
• POR event on VDD supply. If there is no DSBOR
circuit to re-arm the VDD supply POR circuit, the
external VDD supply must be lowered to the
natural arming voltage of the POR circuit.
• DSWDT time-out. When the DSWDT timer times
out, the device exits Deep Sleep.
• RTCC alarm (if RTCEN = 1).
• Assertion (‘0’) of the MCLR pin.
• Assertion of the INT0 pin (if the interrupt was
enabled before Deep Sleep mode was entered).
The polarity configuration is used to determine the
assertion level (‘0’ or ‘1’) of the pin that will cause
an exit from Deep Sleep mode. Exiting from Deep
Sleep mode requires a change on the INT0 pin
while in Deep Sleep mode.
Note: Any interrupt pending, when entering
Deep Sleep mode, is cleared.
Exiting Deep Sleep generally does not retain the state
of the device and is equivalent to a Power-on Reset
(POR) of the device. Exceptions to this include the
RTCC (if present), which remains operational through
the wake-up, the DSGPRx registers and DSWDT.
Wake-up events that occur from the time Deep Sleep
exits, until the time the POR sequence completes, are
not ignored. The DSWAKE register will capture ALL
wake-up events, from DSEN set to RELEASE clear.
The sequence for exiting Deep Sleep mode is:
1. After a wake-up event, the device exits Deep
Sleep and performs a POR. The DSEN bit is
cleared automatically. Code execution resumes
at the Reset vector.
2. To determine if the device exited Deep Sleep,
read the Deep Sleep bit, DPSLP (RCON<10>).
This bit will be set if there was an exit from Deep
Sleep mode. If the bit is set, clear it.
3. Determine the wake-up source by reading the
DSWAKE register.
4. Determine if a DSBOR event occurred during
Deep Sleep mode by reading the DSBOR bit
(DSCON<1>).
5. If application context data has been saved, read
it back from the DSGPR0 and DSGPR1 registers.
6. Clear the RELEASE bit (DSCON<0>).
10.4.3
SAVING CONTEXT DATA WITH THE
DSGPRn REGISTERS
As exiting Deep Sleep mode causes a POR, most
Special Function Registers reset to their default POR
values. In addition, because VCORE power is not sup-
plied in Deep Sleep mode, information in data RAM
may be lost when exiting this mode.
Applications which require critical data to be saved
prior to Deep Sleep may use the Deep Sleep General
Purpose registers, DSGPR0 and DSGPR1, or data
EEPROM (if available). Unlike other SFRs, the
contents of these registers are preserved while the
device is in Deep Sleep mode. After exiting Deep
Sleep, software can restore the data by reading the
registers and clearing the RELEASE bit (DSCON<0>).
10.4.4 I/O PINS IN DEEP SLEEP MODES
During Deep Sleep, the general purpose I/O pins retain
their previous states and the Secondary Oscillator
(SOSC) will remain running, if enabled. Pins that are
configured as inputs (TRISx bit set), prior to entry into
Deep Sleep, remain high-impedance during Deep
Sleep. Pins that are configured as outputs (TRISx bit
clear), prior to entry into Deep Sleep, remain as output
pins during Deep Sleep. While in this mode, they
continue to drive the output level determined by their
corresponding LATx bit at the time of entry into Deep
Sleep.
Once the device wakes back up, all I/O pins continue to
maintain their previous states, even after the device
has finished the POR sequence and is executing
application code again. Pins configured as inputs
during Deep Sleep remain high-impedance, and pins
configured as outputs continue to drive their previous
value. After waking up, the TRIS and LAT registers, and
the SOSCEN bit (OSCCON<1>) are reset. If firmware
modifies any of these bits or registers, the I/O will not
immediately go to the newly configured states. Once
the firmware clears the RELEASE bit (DSCON<0>),
the I/O pins are “released”. This causes the I/O pins to
take the states configured by their respective TRIS and
LAT bit values.
This means that keeping the SOSC running after
waking up requires the SOSCEN bit to be set before
clearing RELEASE.
If the Deep Sleep BOR (DSBOR) is enabled, and a
DSBOR or a true POR event occurs during Deep
Sleep, the I/O pins will be immediately released, similar
to clearing the RELEASE bit. All previous state
information will be lost, including the general purpose
DSGPR0 and DSGPR1 contents.
 2010-2011 Microchip Technology Inc.
DS39996F-page 159