PIC24FJ128GA310-I Datasheet, PDF (237/406 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and nanoWatt XLP Technology

PIC24FJ128GA310 FAMILY
REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
bit 5
ACKDT: Acknowledge Data bit (when operating as I²C master; applicable during master receive)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit
(when operating as I²C master; applicable during master receive)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit.
Hardware is clear at the end of the master Acknowledge sequence.
0 = Acknowledge sequence is not in progress
bit 3
RCEN: Receive Enable bit (when operating as I²C master)
1 = Enables Receive mode for I²C. Hardware is clear at the end of the eighth bit of the master receive
data byte.
0 = Receive sequence is not in progress
bit 2
PEN: Stop Condition Enable bit (when operating as I²C master)
1 = Initiates Stop condition on the SDAx and SCLx pins. Hardware is clear at the end of the master
Stop sequence.
0 = Stop condition is not in progress
bit 1
RSEN: Repeated Start Condition Enable bit (when operating as I²C master)
1 = Initiates Repeated Start condition on the SDAx and SCLx pins. Hardware is clear at the end of the
master Repeated Start sequence.
0 = Repeated Start condition is not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I²C master)
1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at the end of the master Start
sequence.
0 = Start condition is not in progress
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DS39996F-page 237