PIC24FJ128GA310-I Datasheet, PDF (61/406 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and nanoWatt XLP Technology

TABLE 4-26: REAL-TIME CLOCK AND CALENDAR (RTCC) REGISTER MAP
File Name Addr Bit 15 Bit 14
Bit 13
Bit 12
Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
ALRMVAL 0620
Alarm Value Register Window Based on ALRMPTR<1:0>
ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5
RTCVAL 0624
RTCC Value Register Window Based on RTCPTR<1:0>
RCFGCAL 0626 RTCEN
— RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5
RTCPWC 0628 PWCEN PWCPOL PWCPRE PWSPRE RTCLK1 RTCLK0 RTCOUT1 RTCOUT0 —
—
—
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The status of the RCFGCAL and RTCPWR registers on POR is ‘0000’, and on other Resets, it is unchanged.
Bit 4
ARPT4
CAL4
—
Bit 3
ARPT3
CAL3
—
Bit 2
ARPT2
CAL2
—
Bit 1
Bit 0
All
Resets
xxxx
ARPT1 ARPT0 0000
CAL1
—
CAL0
—
xxxx
Note 1
Note 1
TABLE 4-27: DATA SIGNAL MODULATOR (DSM) REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
MDCON
062A MDEN
—
MDSIDL
—
—
—
MDSRC
062C
—
—
—
—
—
—
MDCAR
062E CHODIS CHPOL CHSYNC —
CH3
CH2
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
CH1
—
—
CH0
—
SODIS
CLODIS
MDOE
—
CLPOL
MDSLR MDOPOL
—
—
CLSYNC —
—
MS3
CL3
Bit 2
—
MS2
CL2
Bit 1
—
MS1
CL1
Bit 0
MDBIT
MS0
CL0
All
Resets
0020
000x
0000
TABLE 4-28: COMPARATORS REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
CMSTAT
0630 CMIDL
—
—
—
C3EVT C2EVT C1EVT
—
CVRCON 0632
—
—
—
—
— CVREFP CVREFM1 CVREFM0 CVREN
CM1CON 0634 CON
COE
CPOL
—
—
—
CEVT
COUT EVPOL1
CM2CON 0636 CON
COE
CPOL
—
—
—
CEVT
COUT EVPOL1
CM3CON 0638 CON
COE
CPOL
—
—
—
CEVT
COUT EVPOL1
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
CVROE
EVPOL0
EVPOL0
EVPOL0
—
CVRR
—
—
—
Bit 4
—
CVRSS
CREF
CREF
CREF
Bit 3
—
CVR3
—
—
—
Bit 2
C3OUT
CVR2
—
—
—
Bit 1
C2OUT
CVR1
CCH1
CCH1
CCH1
Bit 0
All
Resets
C1OUT
CVR0
CCH0
CCH0
CCH0
0000
0000
0000
0000
0000