PIC24FJ128GA310-I Datasheet, PDF (81/406 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and nanoWatt XLP Technology

PIC24FJ128GA310 FAMILY
REGISTER 5-3: DMAINTn: DMA CHANNEL n INTERRUPT REGISTER
R-0
U-0
DBUFWF⁽¹⁾
—
bit 15
R/W-0
CHSEL5
R/W-0
CHSEL4
R/W-0
CHSEL3
R/W-0
CHSEL2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
HIGHIF^(1,2) LOWIF^(1,2) DONEIF⁽¹⁾ HALFIF⁽¹⁾ OVRUNIF⁽¹⁾
—
bit 7
R/W-0
CHSEL1
U-0
—
R/W-0
CHSEL0
bit 8
R/W-0
HALFEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-1
bit 0
DBUFWF: Buffered Data Write Flag bit⁽¹⁾
1 = The content of the DMA buffer has not been written to the location specified in DMADST, or
DMASRC in Null Write mode
0 = The content of the DMA buffer has been written to the location specified in DMADST, or DMASRC
in Null Write mode
Unimplemented: Read as ‘0’
CHSEL<5:0>: DMA Channel Trigger Selection bits
See Table 5-1 for a complete list.
HIGHIF: DMA High Address Limit Interrupt Flag bit^(1,2)
1 = The DMA channel has attempted to access an address higher than DMAH, or the upper limit of the
data RAM space.
0 = The DMA channel has not invoked the high address limit interrupt.
LOWIF: DMA Low Address Limit Interrupt Flag bit^(1,2)
1 = The DMA channel has attempted to access the DMA SFR address lower than DMAL, but above
the SFR range (07FFh)
0 = The DMA channel has not invoked the low address limit interrupt
DONEIF: DMA Complete Operation Interrupt Flag bit⁽¹⁾
If CHEN = 1:
1 = The previous DMA session has ended with completion
0 = The current DMA session has not yet completed
If CHEN = 0:
1 = The previous DMA session has ended with completion
0 = The previous DMA session has ended without completion
HALFIF: DMA 50% Water Mark Level Interrupt Flag bit⁽¹⁾
1 = DMACNT has reached the halfway point to 0000h
0 = DMACNT has not reached the halfway point
OVRUNIF: DMA Channel Overrun Flag bit⁽¹⁾
1 = The DMA channel is triggered while it is still completing the operation based on the previous trigger
0 = The overrun condition has not occurred
Unimplemented: Read as ‘0’
HALFEN: Halfway Completion Water Mark bit
1 = Interrupts are invoked when DMACNT has reached its halfway point and at completion
0 = An interrupt is invoked only at the completion of the transfer
Note 1: Setting these flags in software does not generate an interrupt.
2: Testing for address limit violations (DMASRC or DMADST is either greater than DMAH or less than
DMAL) is NOT done before the actual access.
 2010-2011 Microchip Technology Inc.
DS39996F-page 81