PIC18F45J10 Datasheet, PDF (89/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
REGISTER 8-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 R/W-0
U-0
U-0
R/W-0
U-0
OSCFIE CMIE
—
—
BCL1IE
—
bit 7
U-0
R/W-0
—
CCP2IE
bit 0
bit 7
bit 6
bit 5-4
bit 3
bit 2-1
bit 0
OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
CMIE: Comparator Interrupt Enable bit
1 = Enabled
0 = Disabled
Unimplemented: Read as ‘0’
BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module)
1 = Enabled
0 = Disabled
Unimplemented: Read as ‘0’
CCP2IE: CCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 8-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0 R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
SSP2IE BCL2IE
—
—
—
—
—
—
bit 7
bit 0
bit 7
bit 6
bit 5-0
SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit
1 = Enabled
0 = Disabled
BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)
1 = Enabled
0 = Disabled
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 87