PIC18F45J10 Datasheet, PDF (172/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
15.4.6 MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPxCON1 and by setting
the SSPEN bit. In Master mode, the SCLx and SDAx
lines are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I²C bus may be taken when the P bit is
set, or the bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I²C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1. Assert a Start condition on SDAx and SCLx.
2. Assert a Repeated Start condition on SDAx and
SCLx.
3. Write to the SSPxBUF register initiating
transmission of data/address.
4. Configure the I²C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDAx and SCLx.
Note:
The MSSP module, when configured in
I²C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register to
initiate transmission before the Start con-
dition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPxBUF did not occur.
The following events will cause the MSSP Interrupt
Flag bit, SSPxIF, to be set (and MSSP interrupt, if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
FIGURE 15-16: MSSP BLOCK DIAGRAM (I²C™ MASTER MODE)
SDAx
Read
Internal
Data Bus
Write
SSPxBUF
SDAx In
SSPxSR
Shift
Clock
MSb
LSb
SSPM3:SSPM0
SSPxADD<6:0>
Baud
Rate
Generator
SCLx
Start bit, Stop bit,
Acknowledge
Generate
SCLx In
Bus Collision
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCV
Set/Reset S, P, WCOL (SSPxSTAT, SSPxCON1)
Set SSPxIF, BCLxIF
Reset ACKSTAT, PEN (SSPxCON2)
DS39682C-page 170
Preliminary
© 2007 Microchip Technology Inc.