PIC18F45J10 Datasheet, PDF (343/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
APPENDIX A: REVISION HISTORY
Revision A (March 2005)
Original data sheet for PIC18F45J10 family devices.
Revision C (January 2007)
This revision includes updates to the packaging
diagrams.
APPENDIX B: MIGRATION
BETWEEN HIGH-END
DEVICE FAMILIES
Devices in the PIC18F45J10 family and PIC18F4520
families are very similar in their functions and feature
sets. However, there are some potentially important
differences which should be considered when
migrating an application across device families to
achieve a new design goal. These are summarized in
Table B-1. The areas of difference which could be a
major impact on migration are discussed in greater
detail later in this section.
TABLE B-1: NOTABLE DIFFERENCES BETWEEN PIC18F4520 AND PIC18FXXXX FAMILIES
Characteristic
PIC18FXXXX Family
PIC18F4520 Family
Operating Frequency
40 MHz @ 2.15V
Supply Voltage
2.0V-3.6V
Operating Current
Low
Program Memory Endurance
1,000 write/erase cycles (typical)
I/O Sink/Source at 25 mA
PORTB and PORTC only
Input Voltage Tolerance on I/O pins
5.5V on digital only pins
I/O
32
Pull-ups
PORTB
Oscillator Options
Limited options
(EC, HS, fixed 32 kHz INTRC)
Program Memory Retention
10 years (minimum)
Programming Time (Normalized)
156 μs/byte (10 ms/64-byte block)
Programming Entry
Low Voltage, Key Sequence
Code Protection
Single block, all or nothing
Configuration Words
Stored in last 4 words of
Program Memory space
Start-up Time from Sleep
200 μs (typical)
Power-up Timer
Always on
Data EEPROM
BOR
Not available
Simple BOR⁽¹⁾
LVD
Not available
A/D Calibration
Required
In-Circuit Emulation
Not available
TMR3
Second MSSP
Not available
Available⁽²⁾
Note 1: BOR is not available on PIC18LFXXJ10 devices.
2: Available on 40/44-pin devices only.
40 MHz @ 4.2V
2.0V-5.5V
Lower
100,000 write/erase cycles (typical)
All ports
VDD on all I/O pins
36
PORTB
More options (EC, HS, XT, LP, RC,
PLL, flexible INTRC)
40 years (minimum)
15.6 μs/byte (1 ms/64-byte block)
VPP and LVP
Multiple code protection blocks
Stored in Configuration Space,
starting at 300000h
10 μs (typical)
Configurable
Available
Programmable BOR
Available
Not required
Available
Available
Not available
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 341