PIC18F45J10 Datasheet, PDF (329/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
TABLE 23-25: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min Max Units
Conditions
130 TAD
A/D Clock Period
0.7 25.0⁽¹⁾ μs TOSC based, VREF ≥ 2.0V
TBD
1
μs A/D RC mode
131 TCNV Conversion Time
11
12
TAD
(not including acquisition time) (Note 2)
132 TACQ Acquisition Time (Note 3)
1.4
—
μs -40°C to +85°C
TBD
—
μs 0°C ≤ to ≤ +85°C
135 TSWC Switching Time from Convert → Sample
— (Note 4)
Legend:
Note 1:
2:
3:
4:
TBD = To Be Determined
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
ADRES registers may be read on the following TCY cycle.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
On the following cycle of the device clock.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 327