PIC18F45J10 Datasheet, PDF (66/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
FIGURE 5-8:
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
Example Instruction: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When ‘a’ = 0 and f ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is inter-
preted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
locations 060h to 07Fh
(Bank 0) and F80h to FFFh
(Bank 15) of data memory.
Locations below 60h are not
available in this addressing
mode.
When ‘a’ = 0 and f ≤ 5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When ‘a’ = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is inter-
preted as a location in one of
the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
000h
060h
080h
100h
Bank 0
Bank 1
through
Bank 14
F00h
F80h
FFFh
Bank 15
SFRs
Data Memory
000h
080h
100h
Bank 0
Bank 1
through
Bank 14
F00h
F80h
FFFh
Bank 15
SFRs
Data Memory
000h
080h
100h
Bank 0
Bank 1
through
Bank 14
F00h
F80h
FFFh
Bank 15
SFRs
Data Memory
00h
60h
80h
Valid range
for ‘f’
FFh
Access RAM
001001da ffffffff
FSR2H FSR2L
BSR
00000000
001001da ffffffff
DS39682C-page 64
Preliminary
© 2007 Microchip Technology Inc.