PIC18F45J10 Datasheet, PDF (150/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
15.3.2 OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCKx is the clock output)
• Slave mode (SCKx is the clock input)
• Clock Polarity (Idle state of SCKx)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCKx)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Each MSSP consists of a transmit/receive shift register
(SSPxSR) and a buffer register (SSPxBUF). The
SSPxSR shifts the data in and out of the device, MSb
first. The SSPxBUF holds the data that was written to the
SSPxSR until the received data is ready. Once the 8 bits
of data have been received, that byte is moved to the
SSPxBUF register. Then, the Buffer Full detect bit BF
(SSPxSTAT<0>) and the interrupt flag bit SSPxIF are
set. This double-buffering of the received data
(SSPxBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPxBUF register during transmission/reception of data
will be ignored and the Write Collision detect bit, WCOL
(SSPxCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the following
write(s) to the SSPxBUF register completed
successfully.
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the next
byte of data to transfer is written to the SSPxBUF. The
Buffer Full bit, BF (SSPxSTAT<0>), indicates when
SSPxBUF has been loaded with the received data
(transmission is complete). When the SSPxBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. The SSPxBUF must be read and/or
written. If the interrupt method is not going to be used,
then software polling can be done to ensure that a write
collision does not occur. Example 15-1 shows the
loading of the SSP1BUF (SSP1SR) for data
transmission.
The SSPxSR is not directly readable or writable and
can only be accessed by addressing the SSPxBUF
register. Additionally, the SSPxSTAT register indicates
the various status conditions.
EXAMPLE 15-1: LOADING THE SSP1BUF (SSP1SR) REGISTER
LOOP
BTFSS
BRA
MOVF
SSP1STAT, BF
LOOP
SSP1BUF, W
;Has data been received (transmit complete)?
;No
;WREG reg = contents of SSP1BUF
MOVWF RXDATA
;Save in user RAM, if data is meaningful
MOVF TXDATA, W
MOVWF SSP1BUF
;W reg = contents of TXDATA
;New data to xmit
DS39682C-page 148
Preliminary
© 2007 Microchip Technology Inc.