PIC18F45J10 Datasheet, PDF (112/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
FIGURE 9-4:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 9-5:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 9-13: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD⁽¹⁾ RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
LATD⁽¹⁾ PORTD Data Latch Register (Read and Write to Data Latch)
TRISD⁽¹⁾ PORTD Data Direction Control Register
PORTE⁽¹⁾
—
—
—
—
—
RE2
RE1
RE0
LATE⁽¹⁾
—
—
—
—
— PORTE Data Latch Register
(Read and Write to Data Latch)
TRISE⁽¹⁾
IBF
OBF
IBOV PSPMODE —
TRISE2 TRISE1 TRISE0
INTCON
PIR1
PIE1
IPR1
GIE/GIEH PEIE/GIEL
PSPIF⁽¹⁾ ADIF
PSPIE⁽¹⁾ ADIE
PSPIP⁽¹⁾ ADIP
TMR0IE
RCIF
RCIE
RCIP
INT0IE
TXIF
TXIE
TXIP
RBIE
SSP1IF
SSP1IE
SSP1IP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
TMR1IF
TMR1IE
TMR1IP
ADCON1
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
Reset
Values
on page
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DS39682C-page 110
Preliminary
© 2007 Microchip Technology Inc.