PIC18F45J10 Datasheet, PDF(61/358 Page) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

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PIC18F45J10 Datasheet, PDF (61/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

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PIC18F45J10 FAMILY

TABLE 5-2: REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED)

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on Details

POR, BOR on page:

SPBRGH EUSART Baud Rate Generator Register High Byte

0000 0000 45, 192

SPBRG

EUSART Baud Rate Generator Register Low Byte

0000 0000 45, 192

RCREG

EUSART Receive Register

0000 0000 45, 199

TXREG

EUSART Transmit Register

xxxx xxxx 45, 197

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D 0000 0010 45, 188

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D 0000 000x 45, 189

EECON2 EEPROM Control Register 2 (not a physical register)

0000 0000 45, 68

EECON1

â

â

â

FREE

WRERR

WREN

WR

â

---0 x00- 45, 69

IPR3

SSP2IP

BCL2IP

â

â

â

â

â

â

11-- ---- 45, 89

PIR3

SSP2IF

BCL2IF

â

â

â

â

â

â

00-- ---- 45, 85

PIE3

SSP2IE

BCL2IE

â

â

â

â

â

â

00-- ---- 45, 87

IPR2

OSCFIP

CMIP

â

â

BCL1IP

â

â

CCP2IP 11-- 1--1 45, 89

PIR2

OSCFIF

CMIF

â

â

BCL1IF

â

â

CCP2IF 00-- 0--0 45, 85

PIE2

IPR1

PIR1

PIE1

TRISE(2)

TRISD(2)

OSCFIE

PSPIP(2)

PSPIF(2)

PSPIE(2)

CMIE

ADIP

ADIF

ADIE

â

RCIP

RCIF

RCIE

IBF

OBF

IBOV

PORTD Data Direction Control Register

â

TXIP

TXIF

TXIE

PSPMODE

BCL1IE

SSP1IP

SSP1IF

SSP1IE

â

â

CCP1IP

CCP1IF

CCP1IE

TRISE2

â

TMR2IP

TMR2IF

TMR2IE

TRISE1

CCP2IE

TMR1IP

TMR1IF

TMR1IE

TRISE0

00-- 0--0

1111 1111

0000 0000

0000 0000

1111 -111

1111 1111

45, 87

45, 88

45, 84

45, 86

46, 107

46, 103

TRISC

PORTC Data Direction Control Register

1111 1111 46, 100

TRISB

PORTB Data Direction Control Register

1111 1111 46, 97

TRISA

â

â

TRISA5

â

TRISA3

TRISA2

TRISA1

TRISA0 --1- 1111 46, 94

SSP2BUF MSSP2 Receive Buffer/Transmit Register

LATE(2)

â

â

â

â

â

LATD(2)

PORTD Data Latch Register (Read and Write to Data Latch)

PORTE Data Latch Register

(Read and Write to Data Latch)

xxxx xxxx 46, 154

---- -xxx 46, 106

xxxx xxxx 46, 103

LATC

PORTC Data Latch Register (Read and Write to Data Latch)

xxxx xxxx 46, 100

LATB

PORTB Data Latch Register (Read and Write to Data Latch)

xxxx xxxx 46, 97

LATA

SSP2ADD

â

â

PORTA Data Latch Register (Read and Write to Data Latch)

MSSP2 Address Register in I2Câ¢ Slave mode. MSSP2 Baud Rate Reload Register in I2C Master mode.

--xx xxxx 46, 94

0000 0000 46, 154

SSP2STAT

SMP

CKE

D/A

P

S

R/W

UA

BF

0000 0000 46, 146,

156

SSP2CON1 WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0 0000 0000 46, 147,

157

SSP2CON2

PORTE(2)

PORTD(2)

GCEN

â

RD7

ACKSTAT

â

RD6

ACKDT

â

RD5

ACKEN

â

RD4

RCEN

â

RD3

PEN

RE2(2)

RD2

RSEN

RE1(2)

RD1

SEN

RE0(2)

RD0

0000 0000

---- -xxx

xxxx xxxx

46, 158

46, 106

46, 103

PORTC

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0 xxxx xxxx 46, 100

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0 xxxx xxxx 46, 97

PORTA

â

â

RA5

â

RA3

RA2

RA1

RA0 --0- 0000 46, 94

Legend:

Note 1:

2:

x = unknown, u = unchanged, - = unimplemented, q = value depends on condition

See Section 4.4 âBrown-out Reset (BOR) (PIC18F2X1X/4X1X Devices Only)â.

These registers and/or bits are not implemented on 28-pin devices and are read as â0â. Reset values are shown for 40/44-pin devices;

individual unimplemented bits should be interpreted as â-â.

Â© 2007 Microchip Technology Inc.

Preliminary

DS39682C-page 59

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