PIC18F45J10 Datasheet, PDF (118/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
11.1 Timer1 Operation
Timer1 can operate in one of these modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
cycle (FOSC/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
When Timer1 is enabled, the RC1/T1OSI and
RC0/T1OSO/T1CKI pins become inputs. This means
the values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
FIGURE 11-1:
TIMER1 BLOCK DIAGRAM
Timer1 Oscillator
Timer1 Clock Input
On/Off
1
T1OSO/T1CKI
T1OSI
1
FOSC/4
Internal
Clock
0
T1OSCEN⁽¹⁾
TMR1CS
T1CKPS1:T1CKPS0
Prescaler
1, 2, 4, 8
2
Synchronize
Detect
0
Sleep Input
T1SYNC
TMR1ON
Timer1
On/Off
Clear TMR1
(CCP Special Event Trigger)
TMR1L
TMR1
High Byte
Set
TMR1IF
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 11-2:
T1OSO/T1CKI
T1OSI
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
1
FOSC/4
Internal
Clock
0
T1OSCEN⁽¹⁾
TMR1CS
T1CKPS1:T1CKPS0
T1SYNC
TMR1ON
Prescaler
1, 2, 4, 8
2
Synchronize
Detect
0
Sleep Input
Timer1
On/Off
Clear TMR1
(CCP Special Event Trigger)
TMR1L
TMR1
High Byte
8
Set
TMR1IF
on Overflow
Read TMR1L
8
8
Write TMR1L
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39682C-page 116
Preliminary
© 2007 Microchip Technology Inc.