PIC18F45J10 Datasheet, PDF (328/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
TABLE 23-24: A/D CONVERTER CHARACTERISTICS: PIC18F24J10/25J10/44J10/45J10 (INDUSTRIAL)
Param
No.
Symbol
Characteristic
Min
Typ
Max Units
Conditions
A01 NR
Resolution
—
—
10
bit ΔVREF ≥ 3.0V
A03 EIL
Integral Linearity Error
—
—
<±1
LSb ΔVREF ≥ 3.0V
A04 EDL Differential Linearity Error
—
—
<±1
LSb ΔVREF ≥ 3.0V
A06 EOFF Offset Error
—
—
<±3
LSb ΔVREF ≥ 3.0V
A07 EGN
A10 —
Gain Error
Monotonicity
—
—
<±3
Guaranteed⁽¹⁾
LSb ΔVREF ≥ 3.0V
— VSS ≤ VAIN ≤ VREF
A20 ΔVREF Reference Voltage Range
(VREFH – VREFL)
1.8
—
3
—
—
V VDD < 3.0V
—
V VDD ≥ 3.0V
A21 VREFH Reference Voltage High
VSS
—
VREFH
V
A22 VREFL Reference Voltage Low
VSS – 0.3V — VDD – 3.0V V
A25 VAIN Analog Input Voltage
VREFL
—
VREFH
V
A30 ZAIN Recommended Impedance of
—
—
2.2
kΩ
Analog Voltage Source
A50 IREF VREF Input Current⁽²⁾
—
—
5
μA During VAIN acquisition.
—
—
150
μA During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source.
3: Maximum allowed impedance is 8.8 kΩ. This requires higher acquisition time than described in the A/D
chapter.
FIGURE 23-20: A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK
132
A/D DATA
9
8 7 ^{... ...} 2
1
0
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
NEW_DATA
TCY
DONE
Note 1:
2:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
DS39682C-page 326
Preliminary
© 2007 Microchip Technology Inc.