PIC18F45J10 Datasheet, PDF (151/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
15.3.3 ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPxCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPxCON registers and then set the SSPEN bit. This
configures the SDIx, SDOx, SCKx and SSx pins as
serial port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRIS register) appropriately programmed as
follows:
• SDIx is automatically controlled by the SPI module
• SDOx must have TRISC<5> (or TRISD<2>) bit
cleared
• SCKx (Master mode) must have TRISC<3> (or
TRISD<0>) bit cleared
• SCKx (Slave mode) must have TRISC<3> (or
TRISD<0>) bit set
• SSx must have TRISA<5> (or TRISD<3>) bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
15.3.4 TYPICAL CONNECTION
Figure 15-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCKx signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• Master sends dummy data – Slave sends data
FIGURE 15-2:
SPI™ MASTER/SLAVE CONNECTION
SPI™ Master SSPM3:SSPM0 = 00xxb
SDOx
Serial Input Buffer
(SSPxBUF)
SPI™ Slave SSPM3:SSPM0 = 010xb
SDIx
Serial Input Buffer
(SSPxBUF)
Shift Register
(SSPxSR)
MSb
LSb
SDIx
PROCESSOR 1
SCKx
Serial Clock
SDOx
Shift Register
(SSPxSR)
MSb
LSb
SCKx
PROCESSOR 2
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 149