PIC18F45J10 Datasheet, PDF (59/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 43, 48
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000 43, 48
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000 43, 48
STKPTR
STKFUL STKUNF
—
Return Stack Pointer
00-0 0000 43, 49
PCLATU
—
—
—
Holding Register for PC<20:16>
---0 0000 43, 48
PCLATH
Holding Register for PC<15:8>
0000 0000 43, 48
PCL
PC Low Byte (PC<7:0>)
0000 0000 43, 48
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000 43, 70
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 43, 70
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 43, 70
TABLAT
Program Memory Table Latch
0000 0000 43, 70
PRODH
Product Register High Byte
xxxx xxxx 43, 77
PRODL
Product Register Low Byte
xxxx xxxx 43, 77
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF 0000 000x 43, 81
INTCON2
RBPU
INTEDG0 INTEDG1 INTEDG2
—
TMR0IP
—
RBIP 1111 -1-1 43, 82
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF 11-0 0-00 43, 83
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
43, 62
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
43, 62
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
43, 62
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
43, 62
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
43, 62
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte ---- xxxx 43, 62
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx 43, 62
WREG
Working Register
xxxx xxxx 43
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
43, 62
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
43, 62
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
43, 62
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
43, 62
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
43, 62
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte ---- xxxx 43, 62
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx 43, 62
BSR
—
—
—
—
Bank Select Register
---- 0000 43, 53
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
44, 62
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
44, 62
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
44, 62
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
44, 62
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
44, 62
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 44, 62
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx 44, 62
STATUS
—
—
—
N
OV
Z
DC
C
---x xxxx 44, 60
Legend:
Note 1:
2:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
See Section 4.4 “Brown-out Reset (BOR) (PIC18F2X1X/4X1X Devices Only)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 57