PIC18F45J10 Datasheet, PDF (138/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
14.4.4 HALF-BRIDGE MODE
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output signal
is output on the P1A pin, while the complementary PWM
output signal is output on the P1B pin (Figure 14-4). This
mode can be used for half-bridge applications, as shown
in Figure 14-5, or for full-bridge applications where four
power switches are being modulated with two PWM
signals.
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits,
PDC6:PDC0, sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 14.4.6
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTD<5> data latches, the
TRISC<2> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 14-4:
HALF-BRIDGE PWM
OUTPUT
Period
Period
P1A⁽²⁾
Duty Cycle
td
td
P1B⁽²⁾
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
FIGURE 14-5:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
Standard Half-Bridge Circuit (“Push-Pull”)
V+
PIC18F4XJ10
P1A
FET
Driver
FET
Driver
P1B
+
V
-
Load
+
V
-
Half-Bridge Output Driving a Full-Bridge Circuit
PIC18F4X5J10
P1A
P1B
FET
Driver
FET
Driver
V-
V+
Load
DS39682C-page 136
V-
Preliminary
FET
Driver
FET
Driver
© 2007 Microchip Technology Inc.