PIC18F45J10 Datasheet, PDF (289/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
SUBFSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Subtract Literal from FSR
SUBFSR f, k
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSR(f) – k → FSRf
None
1110 1001 ffkk kkkk
The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified by
‘f’.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example:
SUBFSR 2, 23h
Before Instruction
FSR2 = 03FFh
After Instruction
FSR2 = 03DCh
SUBULNK Subtract Literal from FSR2 and Return
Syntax:
SUBULNK k
Operands:
0 ≤ k ≤ 63
Operation:
FSR2 – k → FSR2
(TOS) → PC
Status Affected: None
Encoding:
1110 1001
11kk
kkkk
Description: The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURN is then
executed by loading the PC with the TOS.
The instruction takes two cycles to
execute; a NOP is performed during the
second cycle.
This may be thought of as a special case of
the SUBFSR instruction, where f = 3 (binary
‘11’); it operates only on FSR2.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Decode
No
Operation
Q2
Read
register ‘f’
No
Operation
Q3
Process
Data
No
Operation
Q4
Write to
destination
No
Operation
Example:
SUBULNK 23h
Before Instruction
FSR2 = 03FFh
PC
= 0100h
After Instruction
FSR2 =
PC
=
03DCh
(TOS)
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 287