PIC18F45J10 Datasheet, PDF (202/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
FIGURE 16-7:
RX (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
ASYNCHRONOUS RECEPTION
Start
bit bit 0 bit 1
Start
bit 7/8 Stop bit bit 0
bit
Word 1
RCREG
Start
bit 7/8 Stop bit
bit
Word 2
RCREG
bit 7/8 Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
TABLE 16-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
43
PIR1
PSPIF⁽¹⁾
ADIF
RCIF
TXIF SSP1IF CCP1IF TMR2IF TMR1IF 45
PIE1
PSPIE⁽¹⁾ ADIE
RCIE
TXIE SSP1IE CCP1IE TMR2IE TMR1IE 45
IPR1
PSPIP⁽¹⁾ ADIP
RCIP
TXIP SSP1IP CCP1IP TMR2IP TMR1IP 45
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
45
RCREG EUSART Receive Register
45
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
45
BAUDCON ABDOVF RCIDL
—
SCKP BRG16
—
WUE ABDEN
45
SPBRGH EUSART Baud Rate Generator Register High Byte
45
SPBRG
EUSART Baud Rate Generator Register Low Byte
45
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.
16.2.4 AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller
to wake-up due to activity on the RX/DT line while the
EUSART is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX/DT is disabled and the EUSART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event con-
sists of a high-to-low transition on the RX/DT line. (This
coincides with the start of a Sync Break or a Wake-up
Signal character for the LIN protocol.)
Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 16-8) and asynchronously, if the device is in
Sleep mode (Figure 16-9). The interrupt condition is
cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low-to-
high transition is observed on the RX line following the
wake-up event. At this point, the EUSART module is in
Idle mode and returns to normal operation. This signals
to the user that the Sync Break event is over.
DS39682C-page 200
Preliminary
© 2007 Microchip Technology Inc.