PIC18F45J10 Datasheet, PDF (157/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
15.4 I²C Mode
The MSSP module in I²C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCLx) – RC3/SCK1/SCL1 or
RD0/PSP0/SCK2/SCL2
• Serial data (SDAx) – RC4/SDI1/SDA1 or
RD1/PSP1/SDI2/SDA2
The user must configure these pins as inputs by setting
the TRISC<4:3> or TRISD<1:0> bits.
FIGURE 15-7:
MSSP BLOCK DIAGRAM
(I²C™ MODE)
RC3 or
RD0
RC4 or
RD1
Read
Internal
Data Bus
Write
SSPxBUF reg
Shift
Clock
SSPxSR reg
MSb
LSb
Match Detect Addr Match
SSPxADD reg
Start and
Stop bit Detect
Set, Reset
S, P bits
(SSPxSTAT reg)
Note: Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list
of multiplexed functions.
15.4.1 REGISTERS
The MSSP module has six registers for I²C operation.
These are:
• MSSP Control Register 1 (SSPxCON1)
• MSSP Control Register 2 (SSPxCON2)
• MSSP Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
(SSPxBUF)
• MSSP Shift Register (SSPxSR) – Not directly
accessible
• MSSP Address Register (SSPxADD)
SSPxCON1, SSPxCON2 and SSPxSTAT are the
control and status registers in I²C mode operation. The
SSPxCON1 and SSPxCON2 registers are readable and
writable. The lower 6 bits of the SSPxSTAT are
read-only. The upper 2 bits of the SSPxSTAT are
read/write.
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
SSPxADD register holds the slave device address
when the MSSP is configured in I²C Slave mode.
When the MSSP is configured in Master mode, the
lower seven bits of SSPxADD act as the Baud Rate
Generator reload value.
In receive operations, SSPxSR and SSPxBUF
together create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
During transmission, the SSPxBUF is not
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 155