PIC18F45J10 Datasheet, PDF (237/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
20.2 Watchdog Timer (WDT)
For PIC18F45J10 family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexor, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from 4 ms to 131.072 seconds (2.18 minutes). The
WDT and postscaler are cleared whenever a SLEEP or
CLRWDT instruction is executed, or a clock failure
(primary or Timer1 oscillator) has occurred.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
20.2.1 CONTROL REGISTER
The WDTCON register (Register 20-9) is a readable
and writable register. The SWDTEN bit enables or
disables WDT operation.
FIGURE 20-1:
WDT BLOCK DIAGRAM
SWDTEN
INTRC Oscillator
Enable WDT
INTRC Control
WDT Counter
÷128
CLRWDT
All Device Resets
WDTPS3:WDTPD0
Sleep
Programmable Postscaler ^Reset
1:1 to 1:32,768
WDT
4
Wake-up from
Power-Managed
Modes
WDT
Reset
REGISTER 20-9:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
bit 7
U-0
R/W-0
—
SWDTEN⁽¹⁾
bit 0
bit 7-1
bit 0
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit⁽¹⁾
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note 1: This bit has no effect if the configuration bit, WDTEN, is enabled.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
TABLE 20-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on page
RCON
IPEN
—
—
RI
TO
PD
POR
BOR
44
WDTCON
—
—
—
—
—
—
— SWDTEN
44
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 235