PIC18F45J10 Datasheet, PDF (100/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
TABLE 9-5: PORTB I/O SUMMARY
Pin
Function
TRIS
Setting
I/O
I/O
Type
Description
RB0/INT0/FLT0/
RB0
AN12
RB1/INT1/AN10
INT0
FLT0
AN12
RB1
0
O
DIG LATB<0> data output; not affected by analog input.
1
I
TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.⁽¹⁾
1
I
ST External interrupt 0 input.
1
I
ST PWM Fault input (ECCP1/CCP1 module); enabled in
software.
1
I
ANA A/D input channel 12.⁽¹⁾
0
O
DIG LATB<1> data output; not affected by analog input.
RB2/INT2/AN8
INT1
AN10
RB2
1
I
TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.⁽¹⁾
1
I
ST External interrupt 1 input.
1
I
ANA A/D input channel 10.⁽¹⁾
0
O
DIG LATB<2> data output; not affected by analog input.
RB3/AN9/CCP2
INT2
AN8
RB3
1
I
TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.⁽¹⁾
1
I
ST External interrupt 2 input.
1
I
ANA A/D input channel 8.⁽¹⁾
0
O
DIG LATB<3> data output; not affected by analog input.
1
AN9
1
CCP2⁽²⁾
0
1
RB4/KBI0/AN11
RB4
0
I
TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.⁽¹⁾
I
ANA A/D input channel 9.⁽¹⁾
O
DIG CCP2 compare and PWM output.
I
ST CCP2 capture input
O
DIG LATB<4> data output; not affected by analog input.
1
I
TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.⁽¹⁾
KBI0
1
I
TTL Interrupt-on-change pin.
AN11
1
I
ANA A/D input channel 11.⁽¹⁾
RB5/KBI1/T0CKI/ RB5
C1OUT
0
O
DIG LATB<5> data output.
1
I
TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared.
KBI1
1
I
TTL Interrupt-on-change pin.
T0CKI
1
I
ST Timer0 clock input.
C1OUT
0
O
DIG Comparator 1 output; takes priority over port data.
RB6/KBI2/PGC
RB6
0
O
DIG LATB<6> data output.
RB7/KBI3/PGD
KBI2
PGC
RB7
1
I
TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared.
1
I
TTL Interrupt-on-change pin.
x
I
ST Serial execution (ICSP™) clock input for ICSP and ICD operation.⁽³⁾
0
O
DIG LATB<7> data output.
Legend:
Note 1:
2:
3:
1
I
TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared.
KBI3
PGD
1
I
TTL Interrupt-on-change pin.
x
O
DIG Serial execution data output for ICSP and ICD operation.⁽³⁾
x
I
ST Serial execution data input for ICSP and ICD operation.⁽³⁾
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Configuration on POR is determined by the PBADEN configuration bit. Pins are configured as analog inputs by default
when PBADEN is set and digital inputs when PBADEN is cleared.
Alternate assignment for CCP2 when the CCP2MX configuration bit is ‘0’. Default assignment is RC1.
All other pin functions are disabled when ICSP or ICD are enabled.
DS39682C-page 98
Preliminary
© 2007 Microchip Technology Inc.